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riscv/rocket-chip
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f35a6a574f3386d282f9fcd9ef1fd692fe9e9c1c
rocket-chip/uncore/src/main/scala
T
History
Henry Cook f35a6a574f Add a queue on released data coming in to L2
2015-03-16 13:25:01 -07:00
..
bigmem.scala
Removed broken or unfinished modules, new MemPipeIO converter
2014-09-24 15:11:24 -07:00
broadcast.scala
Fix BroadcastHub AcquiteTracker allocation bug and clean up tracker wiring
2015-03-15 23:10:51 -07:00
cache.scala
Add a queue on released data coming in to L2
2015-03-16 13:25:01 -07:00
coherence.scala
L2 Writeback bugfix
2015-03-10 01:15:03 -07:00
consts.scala
Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
2015-02-01 20:37:16 -08:00
directory.scala
New metadata-based coherence API
2015-02-28 17:32:03 -08:00
htif.scala
Use entire 12-bit CSR address
2015-03-14 02:15:24 -07:00
memserdes.scala
separate queues for resp tag and data
2015-03-15 17:58:17 -07:00
metadata.scala
New metadata-based coherence API
2015-02-28 17:32:03 -08:00
network.scala
%s/master/manager/g + better comments
2014-12-29 22:55:58 -08:00
package.scala
add LICENSE
2014-09-12 15:31:38 -07:00
slowio.scala
add LICENSE
2014-09-12 15:31:38 -07:00
tilelink.scala
No more self-probes required
2015-03-16 00:09:38 -07:00
uncore.scala
clean up incoherent and probe flags
2015-03-12 16:22:14 -07:00
util.scala
Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
2015-02-01 20:37:16 -08:00
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