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rocket-chip/src/main/scala
Andrew Waterman aad75f2285 Implement misa.C proposal
This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
2018-02-22 15:12:19 -08:00
..
amba Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
config config: remove deprecated Parameters.root 2018-01-30 11:52:44 -08:00
coreplex Preserve WithRV32 behavior: FLEN = 32 2018-02-20 18:28:47 -08:00
devices debug: get beatBytes from pbus, not XLen 2018-02-20 16:16:39 -08:00
diplomacy diplomacy: run user instantiate() method after nodes are initialized (#1198) 2018-01-18 14:57:47 -08:00
groundtest tile: BaseTileModule => BaseTileModuleImp 2018-01-02 17:55:54 -08:00
interrupts diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
jtag JTAG: Use new withClock way of overriding clocks (#1072) 2018-01-17 13:59:05 -08:00
regmapper RegFieldDesc: don't put characters into names that need to be sanitized 2018-02-15 13:25:06 -08:00
rocket Implement misa.C proposal 2018-02-22 15:12:19 -08:00
system support testing RV32D configs 2018-02-20 16:16:39 -08:00
tile Add FPUParams.fLen option, decoupled from xLen 2018-02-20 16:16:39 -08:00
tilelink RegFieldDesc: fix the output produced for undescribed registers 2018-02-16 10:24:12 -08:00
unittest Emit plusArgs for unit tests 2018-01-15 17:54:40 -05:00
util ElaborationArtefacts: revert unintentional change 2018-02-15 14:23:54 -08:00