Andrew Waterman 76af15a6ff Fix FPU control bug for div/sqrt ...

I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.

2017-06-09 15:51:06 -07:00

..

BaseTile.scala

tile: add tileBus xbar

2017-05-16 16:12:01 -07:00

Core.scala

new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels

2017-04-27 18:17:31 -07:00

FPU.scala

Fix FPU control bug for div/sqrt

2017-06-09 15:51:06 -07:00

Interrupts.scala

local_interrupts: Correct off-by-1 if there is no SEIP

2017-05-02 21:55:25 -07:00

L1Cache.scala

Separate tag ECC and data ECC options (#761)

2017-05-23 12:51:48 -07:00

LegacyRoCC.scala

rocc: fix RoccExampleConfig

2017-05-16 16:44:53 -07:00

Package.scala

Heterogeneous Tiles (#550)

2017-02-09 13:59:09 -08:00