76af15a6ff
I was examining a WB-stage control signal instead of a MEM-stage control signal. I refactored the code to group the signals together, so that this sort of bug is less likely going forward. |
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| .. | ||
| BaseTile.scala | ||
| Core.scala | ||
| FPU.scala | ||
| Interrupts.scala | ||
| L1Cache.scala | ||
| LegacyRoCC.scala | ||
| Package.scala | ||