62 lines
1.7 KiB
Scala
62 lines
1.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package tile
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import Chisel._
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import config.Parameters
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import uncore.tilelink2.{IntSinkNode, IntSinkPortSimple}
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import util._
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class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
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val debug = Bool()
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val mtip = Bool()
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val msip = Bool()
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val meip = Bool()
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val seip = usingVM.option(Bool())
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val lip = Vec(coreParams.nLocalInterrupts, Bool())
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}
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// Use diplomatic interrupts to external interrupts from the coreplex into the tile
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trait HasExternalInterrupts extends HasTileParameters {
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implicit val p: Parameters
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val module: HasExternalInterruptsModule
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val intNode = IntSinkNode(IntSinkPortSimple())
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// TODO: the order of the following two functions must match, and
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// also match the order which things are connected to the
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// per-tile crossbar in coreplex.HasRocketTiles
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// debug, msip, mtip, meip, seip, lip offsets in CSRs
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def csrIntMap: List[Int] = {
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val nlips = tileParams.core.nLocalInterrupts
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val seip = if (usingVM) Seq(9) else Nil
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List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16)
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}
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}
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trait HasExternalInterruptsBundle {
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val outer: HasExternalInterrupts
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val interrupts = outer.intNode.bundleIn
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}
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trait HasExternalInterruptsModule {
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val outer: HasExternalInterrupts
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val io: HasExternalInterruptsBundle
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// go from flat diplomatic Interrupts to bundled TileInterrupts
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def decodeCoreInterrupts(core: TileInterrupts) {
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val async_ips = Seq(core.debug)
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val periph_ips = Seq(
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core.msip,
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core.mtip,
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core.meip)
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val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil
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val core_ips = core.lip
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(async_ips ++ periph_ips ++ seip ++ core_ips).zip(io.interrupts(0)).foreach { case(c, i) => c := i }
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}
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}
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