| .. |
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Arbiter.scala
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tilelink2: improve round robin arbiter QoR
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2017-06-01 15:34:40 -07:00 |
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AsyncCrossing.scala
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unittests: accept a configurable number of transactions to run
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2017-05-17 14:02:59 -07:00 |
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AtomicAutomata.scala
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diplomacy: improve PMA circuit QoR
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2017-06-01 15:30:20 -07:00 |
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Atomics.scala
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tilelink2: add a generic TL2 atomic evaulation unit
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2017-04-14 15:13:39 -07:00 |
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Broadcast.scala
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diplomacy: require masters to have a name
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2017-06-02 15:52:20 -07:00 |
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Buffer.scala
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diplomacy: BufferParams can now directly create a Queue
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2017-06-14 13:47:37 -07:00 |
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Bundles.scala
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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CacheCork.scala
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TLCacheCork: unsafe flag now _really_ unsafe (#760)
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2017-05-22 19:37:11 -07:00 |
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Delayer.scala
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TLDelayer: insert noise on invalid cycles
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2017-03-11 02:53:43 -08:00 |
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Edges.scala
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tilelink2: define is{Request,Response} based on spec
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2017-03-20 13:41:02 -07:00 |
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Error.scala
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devices: add reg-names to most devices
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2017-06-28 15:06:16 -07:00 |
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Example.scala
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uncore: add DTS meta-data for devices
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2017-03-02 21:19:22 -08:00 |
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FIFOFixer.scala
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tilelink2: FIFOFixer should NOT change client request status
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2017-05-01 22:53:41 -07:00 |
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Filter.scala
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uncore: switch to new diplomacy Node API
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2017-01-29 15:54:45 -08:00 |
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Fragmenter.scala
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diplomacy: require masters to have a name
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2017-06-02 15:52:20 -07:00 |
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Fuzzer.scala
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diplomacy: require masters to have a name
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2017-06-02 15:52:20 -07:00 |
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HintHandler.scala
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unittests: accept a configurable number of transactions to run
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2017-05-17 14:02:59 -07:00 |
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IntNodes.scala
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graphML: reverse interrupt arrows
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2017-04-14 18:09:14 -07:00 |
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Isolation.scala
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tilelink2: split suportsAcquire into T and B variants
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2017-01-19 19:07:13 -08:00 |
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Legacy.scala
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diplomacy: require masters to have a name
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2017-06-02 15:52:20 -07:00 |
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Metadata.scala
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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Monitor.scala
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tilelink2: TLMonitor will not create giant wires
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2017-06-13 16:58:22 -07:00 |
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NodeNumberer.scala
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NodeNumberer: add an adapter to map inter-chip fabrics
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2017-06-02 20:42:17 -07:00 |
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Nodes.scala
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diplomacy: a type of connect that always disables monitors (#828)
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2017-06-28 21:48:10 -07:00 |
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package.scala
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Move RoCC interface to Diplomacy and TL2 (#807)
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2017-06-22 12:07:09 -07:00 |
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Parameters.scala
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diplomacy: add RWXC permissions also to ResourceMappings
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2017-06-28 15:06:19 -07:00 |
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RAMModel.scala
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tilelink2: RAMModel, use CRC16 to check AMO response
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2017-04-14 15:13:40 -07:00 |
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RationalCrossing.scala
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unittests: accept a configurable number of transactions to run
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2017-05-17 14:02:59 -07:00 |
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RegisterRouter.scala
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devices: add reg-names to most devices
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2017-06-28 15:06:16 -07:00 |
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RegisterRouterTest.scala
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unittests: accept a configurable number of transactions to run
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2017-05-17 14:02:59 -07:00 |
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Repeater.scala
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copyright: ran scripts/modify-copyright
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2016-11-27 22:15:43 -08:00 |
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SourceShrinker.scala
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diplomacy: require masters to have a name
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2017-06-02 15:52:20 -07:00 |
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Splitter.scala
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isp: passthru based on edgesOut = edgesIn (#814)
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2017-06-22 21:23:49 -07:00 |
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SRAM.scala
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SRAM: MemoryDevices use .reg (not .reg("mem")) (#835)
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2017-06-29 19:07:12 -07:00 |
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TestRAM.scala
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SRAM: MemoryDevices use .reg (not .reg("mem")) (#835)
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2017-06-29 19:07:12 -07:00 |
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ToAHB.scala
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diplomacy: require masters to have a name
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2017-06-02 15:52:20 -07:00 |
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ToAPB.scala
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diplomacy: require masters to have a name
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2017-06-02 15:52:20 -07:00 |
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ToAXI4.scala
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tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822)
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2017-06-26 17:54:17 -07:00 |
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WidthWidget.scala
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unittests: accept a configurable number of transactions to run
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2017-05-17 14:02:59 -07:00 |
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Xbar.scala
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Merge pull request #757 from freechipsproject/isp-port
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2017-06-15 13:07:19 -07:00 |
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Zero.scala
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TLZero: include a version number
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2017-06-28 15:12:46 -07:00 |
