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rocket-chip/src/main/scala/uncore/tilelink2
2017-06-29 19:07:12 -07:00
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Arbiter.scala tilelink2: improve round robin arbiter QoR 2017-06-01 15:34:40 -07:00
AsyncCrossing.scala unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
AtomicAutomata.scala diplomacy: improve PMA circuit QoR 2017-06-01 15:30:20 -07:00
Atomics.scala tilelink2: add a generic TL2 atomic evaulation unit 2017-04-14 15:13:39 -07:00
Broadcast.scala diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Buffer.scala diplomacy: BufferParams can now directly create a Queue 2017-06-14 13:47:37 -07:00
Bundles.scala rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
CacheCork.scala TLCacheCork: unsafe flag now _really_ unsafe (#760) 2017-05-22 19:37:11 -07:00
Delayer.scala TLDelayer: insert noise on invalid cycles 2017-03-11 02:53:43 -08:00
Edges.scala tilelink2: define is{Request,Response} based on spec 2017-03-20 13:41:02 -07:00
Error.scala devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
Example.scala uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
FIFOFixer.scala tilelink2: FIFOFixer should NOT change client request status 2017-05-01 22:53:41 -07:00
Filter.scala uncore: switch to new diplomacy Node API 2017-01-29 15:54:45 -08:00
Fragmenter.scala diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Fuzzer.scala diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
HintHandler.scala unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
IntNodes.scala graphML: reverse interrupt arrows 2017-04-14 18:09:14 -07:00
Isolation.scala tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Legacy.scala diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Metadata.scala rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
Monitor.scala tilelink2: TLMonitor will not create giant wires 2017-06-13 16:58:22 -07:00
NodeNumberer.scala NodeNumberer: add an adapter to map inter-chip fabrics 2017-06-02 20:42:17 -07:00
Nodes.scala diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
package.scala Move RoCC interface to Diplomacy and TL2 (#807) 2017-06-22 12:07:09 -07:00
Parameters.scala diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
RAMModel.scala tilelink2: RAMModel, use CRC16 to check AMO response 2017-04-14 15:13:40 -07:00
RationalCrossing.scala unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
RegisterRouter.scala devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
RegisterRouterTest.scala unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
Repeater.scala copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
SourceShrinker.scala diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Splitter.scala isp: passthru based on edgesOut = edgesIn (#814) 2017-06-22 21:23:49 -07:00
SRAM.scala SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) 2017-06-29 19:07:12 -07:00
TestRAM.scala SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) 2017-06-29 19:07:12 -07:00
ToAHB.scala diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
ToAPB.scala diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
ToAXI4.scala tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) 2017-06-26 17:54:17 -07:00
WidthWidget.scala unittests: accept a configurable number of transactions to run 2017-05-17 14:02:59 -07:00
Xbar.scala Merge pull request #757 from freechipsproject/isp-port 2017-06-15 13:07:19 -07:00
Zero.scala TLZero: include a version number 2017-06-28 15:12:46 -07:00