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rocket-chip/src/main/scala
Megan Wachs 76a1ae667f PLIC: (undefZero=true) Don't allow addresses to alias
While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
2017-07-06 17:57:08 -07:00
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config Configs: use a uniform syntax without Match exceptions (#507) 2017-01-13 14:41:19 -08:00
coreplex diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
diplomacy diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
groundtest groundtest: fix test ram width 2017-06-20 18:11:22 -07:00
jtag jtag: make it easier to assign MFR ID externally 2017-04-14 01:03:11 -07:00
junctions debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. 2017-03-27 21:25:37 -07:00
regmapper ReduceOthers: remove constants from the balanced AND tree 2017-06-23 00:28:05 -07:00
rocket Merge pull request #849 from freechipsproject/l2-tlb 2017-07-06 13:03:06 -07:00
rocketchip diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
tile Add L2 TLB option 2017-07-06 01:19:18 -07:00
uncore PLIC: (undefZero=true) Don't allow addresses to alias 2017-07-06 17:57:08 -07:00
unittest unittest: balance the run times of the tests 2017-05-17 14:02:59 -07:00
util Add grouped method to AugmentedUInt, like Seq.grouped 2017-06-28 02:09:18 -07:00