rocket-chip

Arbiters.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

AsyncBundle.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

AsyncQueue.scala

Add 1-deep synchronizer register for output of AsyncQueue

2017-08-28 17:18:54 -07:00

AsyncResetReg.scala

synchronizers: New chisel ways of cloning type and use simpler lambda function

2017-08-30 12:11:14 -07:00

Broadcaster.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

ClockDivider.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

Counters.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

CRC.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

Crossing.scala

util: delete old long-deprecated crossing code

2017-10-26 13:58:52 -07:00

DescribedReg.scala

RegFieldDesc: Add utilities for generating and describing registers at the same time.

2018-03-05 12:02:42 -08:00

ECC.scala

rocket: base trait for reporting ecc errors

2017-09-21 14:58:47 -07:00

Frequency.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

GeneratorUtils.scala

coreplex => subsystem

2018-02-21 14:42:24 -08:00

GenericParameterizedBundle.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

HellaQueue.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

HeterogeneousBag.scala

Bump chisel and firrtl (#1232 )

2018-03-01 15:19:12 -08:00

IdentityModule.scala

util: add the IdentityModule, useful to dedup wires

2017-09-07 16:03:35 -07:00

LatencyPipe.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

LCG.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

Misc.scala

Bump chisel and firrtl (#1232 )

2018-03-01 15:19:12 -08:00

MultiWidthFifo.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

package.scala

util: augment String and use to name couplers

2018-02-21 14:43:47 -08:00

PlusArg.scala

Explicitly name PlusArg serializers as *_cHeader

2018-01-15 17:00:12 -05:00

PositionalMultiQueue.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

Property.scala

Replace Parameters in cover with globally setable implementation (#1200 )

2018-01-18 14:45:36 -08:00

PSDTestMode.scala

test_mode_reset: use a cleaner interface with bundles and options instead of individual signals

2017-09-15 12:30:39 -07:00

RationalCrossing.scala

RationalCrossing: use ShiftQueues

2017-09-07 16:03:34 -07:00

ReduceOthers.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

ReorderQueue.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

Repeater.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00

Replacement.scala

Make PseudoLRU policy support non-power-of-2 sizes

2017-11-01 01:47:23 -07:00

ResetCatchAndSync.scala

ResetCatchAndSync: work also in the context of a RawModule (#1202 )

2018-01-19 19:45:52 -08:00

ROMGenerator.scala

tilelink: add mask rom

2017-07-31 21:34:04 -07:00

ShiftQueue.scala

ShiftQueue: added a helper object

2017-09-07 16:03:34 -07:00

ShiftReg.scala

Support SynchronizerShiftReg(sync = 0)

2017-09-20 00:05:07 -07:00

Timer.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845 )

2017-07-07 10:48:16 -07:00