Wesley W. Terpstra b1cacc56ad SystemBus: restore correct order of FIFOFixer and Buffer		2017-09-05 16:41:39 -07:00
..
BaseCoreplex.scala	coreplex: change AsynchronousCrossing.sync default to 3	2017-07-27 15:44:51 -07:00
Configs.scala	tilelink: allow insertion of TLDelayer on TLBus outward node	2017-08-07 16:43:06 -07:00
FrontBus.scala	FrontBus: FIFOFixer should not have a buffer between it and Xbar	2017-09-05 16:27:57 -07:00
InterruptBus.scala	Combine Coreplex and System Module Hierarchies (#875)	2017-07-23 08:31:04 -07:00
MemoryBus.scala	coreplex: allow buffer chains on certain bus ports	2017-09-05 15:03:36 -07:00
PeripheryBus.scala	sbus => pbus: 2 buffers should already be enough	2017-09-05 15:03:38 -07:00
Ports.scala	Combine Coreplex and System Module Hierarchies (#875)	2017-07-23 08:31:04 -07:00
ResetVector.scala	tilelink: add mask rom	2017-07-31 21:34:04 -07:00
RocketCoreplex.scala	coreplex: allow buffer chains on certain bus ports	2017-09-05 15:03:36 -07:00
RTC.scala	coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887)	2017-07-25 00:55:55 -07:00
SystemBus.scala	SystemBus: restore correct order of FIFOFixer and Buffer	2017-09-05 16:41:39 -07:00