53dfc5e9be
This assertion made sure the D$ controller was able to write the tag RAM when a cache line was refilled. However, it is benign if it fails to do so: the metadata is invalid at this point, so the miss will simply happen a second time. This happens when resolving a tag ECC error during hit-under-miss. |
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| .. | ||
| amba | ||
| config | ||
| coreplex | ||
| devices | ||
| diplomacy | ||
| groundtest | ||
| jtag | ||
| regmapper | ||
| rocket | ||
| system | ||
| tile | ||
| tilelink | ||
| unittest | ||
| util | ||