Andrew Waterman 53dfc5e9be Remove overzealous assertion (#987) ...

This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.

2017-09-07 18:17:56 -07:00

..

amba

tilelink: Error device supports Acquire

2017-07-27 18:32:58 -07:00

config

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

coreplex

SystemBus: restore correct order of FIFOFixer and Buffer

2017-09-05 16:41:39 -07:00

devices

SystemBus: use a full buffer on slaves

2017-08-26 02:47:04 -07:00

diplomacy

TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer.

2017-08-29 10:36:46 -07:00

groundtest

chiplink: adjust bus view to include the splitter (#886)

2017-07-24 21:41:17 -07:00

jtag

Jtagresettobool - add explicit toBool cast now required on reset. (#984)

2017-09-06 09:49:47 -07:00

regmapper

add cloneType to RegisterWriteIO and RegisterReadIO (#874)

2017-07-18 18:52:31 -07:00

rocket

Remove overzealous assertion (#987)

2017-09-07 18:17:56 -07:00

system

tilelink: add mask rom

2017-07-31 21:34:04 -07:00

tile

coreplex: allow buffer chains on certain bus ports

2017-09-05 15:03:36 -07:00

tilelink

Merge remote-tracking branch 'origin/master' into async_reg

2017-09-06 11:07:19 -07:00

unittest

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

util

synchronizers: I learn how foldRight works

2017-09-07 10:48:27 -07:00