| .. |
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Bundles.scala
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tilelink2: rename wmask => mask since it also applies to reads
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2016-09-05 20:58:39 -07:00 |
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Edges.scala
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tilelink2: rename Operations to Edges (as it only includes Edges)
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2016-09-05 20:58:39 -07:00 |
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GPIO.scala
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tilelink2: AddressSet always has an assigned base address
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2016-09-05 20:58:39 -07:00 |
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HintHandler.scala
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tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp
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2016-09-05 20:58:39 -07:00 |
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LazyModule.scala
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tilelink2: decouple BaseNode from TileLink bus (so it can be reused)
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2016-09-05 20:58:39 -07:00 |
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Legacy.scala
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tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp
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2016-09-05 20:58:39 -07:00 |
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Monitor.scala
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tilelink2: rename wmask => mask since it also applies to reads
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2016-09-05 20:58:39 -07:00 |
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Nodes.scala
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tilelink2: add an IdentityNode for adapters that change nothing
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2016-09-05 20:58:39 -07:00 |
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Parameters.scala
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tilelink2: AddressSet always has an assigned base address
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2016-09-05 20:58:39 -07:00 |
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RegField.scala
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tilelink2: refactor RegField into interface and implementation
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2016-09-05 20:58:39 -07:00 |
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RegisterRouter.scala
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tilelink2: AddressSet always has an assigned base address
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2016-09-05 20:58:39 -07:00 |
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RegMapper.scala
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tilelink2: refactor RegField into interface and implementation
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2016-09-05 20:58:39 -07:00 |
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SRAM.scala
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tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp
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2016-09-05 20:58:39 -07:00 |
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TLNodes.scala
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tilelink2: add an IdentityNode for adapters that change nothing
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2016-09-05 20:58:39 -07:00 |
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Xbar.scala
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tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp
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2016-09-05 20:58:39 -07:00 |
