riscv/rocket-chip
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4389b9edb0
rocket-chip/uncore/src/main/scala
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Henry Cook 4389b9edb0 tilelink parameter tweak: addrBits now a constant
2015-10-20 15:00:30 -07:00
..
amoalu.scala Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU. 2015-10-16 19:11:06 -07:00
broadcast.scala simplify TileLinkParameters with Option 2015-10-16 18:24:38 -07:00
cache.scala Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU. 2015-10-16 19:11:06 -07:00
coherence.scala refactor tilelink params 2015-10-14 12:13:37 -07:00
consts.scala Let isRead be true for store-conditional 2015-09-25 15:28:02 -07:00
directory.scala First pages commit 2015-04-29 13:18:26 -07:00
ecc.scala Chisel3 compatibility: use >>Int instead of >>UInt 2015-08-04 13:15:17 -07:00
htif.scala refactor tilelink params 2015-10-14 12:13:37 -07:00
metadata.scala refactor tilelink params 2015-10-14 12:13:37 -07:00
network.scala Removed all traces of params 2015-10-14 00:23:28 -07:00
package.scala First pages commit 2015-04-29 13:18:26 -07:00
rtc.scala GlobalAddrMap 2015-10-14 00:23:28 -07:00
scr.scala Removed all traces of params 2015-10-14 00:23:28 -07:00
tilelink.scala tilelink parameter tweak: addrBits now a constant 2015-10-20 15:00:30 -07:00
uncore.scala refactor tilelink params 2015-10-14 12:13:37 -07:00
util.scala Removed all traces of params 2015-10-14 00:23:28 -07:00