Yunsup Lee 09e29e8fe0 add zscale ...

only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now

2015-07-07 20:38:47 -07:00

..

.gitignore

Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes

2013-08-19 19:54:41 -07:00

build.properties

add chisel and hardfloat back as sub-projects, bump other sub-projects

2013-09-26 12:01:46 -07:00

build.scala

add zscale

2015-07-07 20:38:47 -07:00

plugins.sbt

Massive update containing several months of changes from the now-defunct private chip repo.

2015-07-02 14:43:30 -07:00