| .. |
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Buffer.scala
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tilelink2 Buffer: support an unlimited number of channels
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2016-09-12 10:32:24 -07:00 |
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Bundles.scala
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tilelink2 Bundles: fix wrong sink width!
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2016-09-08 13:47:40 -07:00 |
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Edges.scala
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[tilelink2] Edges: add size to addr_lo.
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2016-09-12 16:58:09 -07:00 |
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Example.scala
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Merge remote-tracking branch 'origin/master' into black_box_regs
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2016-09-09 13:12:52 -07:00 |
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Fragmenter.scala
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tilelink2 Fragmenter: bugfix using D.hasData
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2016-09-12 16:58:21 -07:00 |
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Fuzzer.scala
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Initial version of fuzzer and simple ram fuzz test
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2016-09-12 10:32:45 -07:00 |
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HintHandler.scala
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tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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2016-09-08 23:06:59 -07:00 |
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IntNodes.scala
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tilelink2 IntNodes: record interrupt ranges in parameters
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2016-09-08 18:51:43 -07:00 |
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LazyModule.scala
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tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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2016-09-08 23:06:59 -07:00 |
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Legacy.scala
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tilelink2 Legacy: it's only an error if it's valid (#264)
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2016-09-08 21:09:40 -07:00 |
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Monitor.scala
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[tilelink2] Monitor: Allow zero-mask PutPartials
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2016-09-12 17:00:50 -07:00 |
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Nodes.scala
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tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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2016-09-08 23:06:59 -07:00 |
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package.scala
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tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
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2016-09-08 21:34:20 -07:00 |
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Parameters.scala
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tilelink2 Parameters: fix width=1 address truncation bug
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2016-09-12 10:32:24 -07:00 |
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RAMModel.scala
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tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible
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2016-09-12 10:32:25 -07:00 |
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RegField.scala
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Merge remote-tracking branch 'origin/master' into black_box_regs
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2016-09-09 13:12:52 -07:00 |
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RegisterRouter.scala
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tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests
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2016-09-12 10:32:24 -07:00 |
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RegisterRouterTest.scala
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tilelink2 RegisterRouter: add RegField test patterns
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2016-09-12 10:32:25 -07:00 |
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RegMapper.scala
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tilelink2: ensure RegFields don't exceed their bounds
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2016-09-05 20:58:40 -07:00 |
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SRAM.scala
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TL2 WidthWidget (#258)
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2016-09-08 10:38:38 -07:00 |
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TestGraphs.scala
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playground for making different DAGs to use as DUTs
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2016-09-12 10:32:45 -07:00 |
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TLNodes.scala
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tilelink2: refactor address into addr_hi on ABC and addr_lo on CD
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2016-09-06 23:46:44 -07:00 |
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WidthWidget.scala
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tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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2016-09-08 23:06:59 -07:00 |
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Xbar.scala
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tilelink2: refactor address into addr_hi on ABC and addr_lo on CD
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2016-09-06 23:46:44 -07:00 |
