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riscv/rocket-chip
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Code Releases Activity
143 Commits 1 Branch 0 Tags
ffda0e41a99e3f344d08e43516ee446d0f28c4b0
Commit Graph
9 Commits
Author SHA1 Message Date
Andrew Waterman ffda0e41a9 parameterize width of MemSerdes/MemDesser 2012-10-18 16:56:36 -07:00
Henry Cook 9df5cfa552 Factored out tilelink classes 2012-10-16 14:26:33 -07:00
Henry Cook 8509cda813 Refined traits for use with rocket asserts, added UncoreConfiguration to handle ntiles 2012-10-16 13:58:18 -07:00
Henry Cook 1418604bf0 new constants organization 2012-10-15 18:52:48 -07:00
Huy Vo 08ab076217 forgot to change package + using fromBits in memserdes instead of manual unpacking 2012-10-10 15:42:39 -07:00
Huy Vo 9610622ab0 moving memserdes + slowio into src 2012-10-10 12:41:11 -07:00
Andrew Waterman 3973aef938 handle structural hazard on LLC tags 2012-10-09 18:04:55 -07:00
Huy Vo 2413763f3d henry's uncore and rocket changes for new xact types 2012-10-01 16:05:37 -07:00
Huy Vo fa8075570a move srcs into src dir, factoring out uncore consts into consts 2012-09-27 12:59:45 -07:00
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