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Commit Graph

17 Commits

Author SHA1 Message Date
Megan Wachs
e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
Henry Cook
d096fd206b
coreplex: WithStatelessBridge => WithIncoherentTiles (#1092) 2017-11-07 13:47:56 -08:00
Henry Cook
b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params
Improvements wrt connecting RocketTiles to SystemBus
2017-10-11 17:12:03 -07:00
Wesley W. Terpstra
b566ffedea system: fix DefaultFPGAConfig (#1047)
It was missing cores. Fixes #736.
2017-10-11 10:48:41 -07:00
Wesley W. Terpstra
5d62c321f4 generator: create annotation file 2017-10-10 23:23:06 -07:00
Henry Cook
75345b6048 rocket: don't remove ports on top module 2017-10-10 21:28:59 -07:00
Henry Cook
37406706b4 coreplex: move CacheCork in front of SBus
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
2017-10-10 16:24:32 -07:00
Henry Cook
8da7aabd51 tile: supply hartid from RocketTileParams
make WithNCores partial configs override rather than append more tiles
2017-10-05 00:31:53 -07:00
Henry Cook
45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
2017-10-05 00:26:44 -07:00
Henry Cook
d33737802a util: add DontTouch trait with dontTouchPorts method 2017-10-02 19:36:34 -07:00
Henry Cook
b86f4b9bb7 config: use Field defaults over Config defaults
Also rename some keys that had the same class name as their value's class name.
2017-09-13 11:25:42 -07:00
Henry Cook
a7540d35b7 ports: use BigInts instead of Longs and the new x"..." context 2017-09-13 11:25:42 -07:00
Yunsup Lee
6ef8ee5d4d tilelink: add mask rom 2017-07-31 21:34:04 -07:00
Wesley W. Terpstra
2e4f1611ed tilelink: Error device supports Acquire
We need this if we want to divert traffic to it from a TL-C slave.
2017-07-27 18:32:58 -07:00
Andrew Waterman
3ced04b70a Mix in trait to connect global_reset_vector 2017-07-25 15:19:16 -07:00
Yunsup Lee
c9e467a668 coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887) 2017-07-25 00:55:55 -07:00
Henry Cook
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00