riscv/rocket-chip
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5 Commits
Author SHA1 Message Date
Wesley W. Terpstra 31b72625aa ahb: allow no-ops to progress also when a slave is !hready 2016-06-09 10:41:12 -07:00
Wesley W. Terpstra 7014eef339 ahb: fix bugs found using comparatortest 2016-06-09 10:41:11 -07:00
Wesley W. Terpstra 11b3cee07a Ahb tweaks (#50) 
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
 2016-06-01 16:42:39 -07:00
Wesley W. Terpstra 7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Wesley W. Terpstra a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts 2016-05-24 14:58:27 -07:00