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Author	SHA1	Message	Date
Colin SchmidtandAndrew Waterman	2c325151bf	pass invalidate_lr through simple cache interface (#45)	2016-06-09 17:22:36 -07:00
Colin SchmidtandAndrew Waterman	8516e38eb2	remove implicit modulo addressing in FPU (#44)	2016-06-09 11:33:33 -07:00
Colin Schmidt	90991014a0	Merge pull request #19 from ucb-bar/multirocc ... Add support for multiple RoCC accelerators	2015-11-28 08:56:04 -05:00