10 Commits

Include renames

Author	SHA1	Message	Date
Henry CookandWesley W. Terpstra	4af437fdab	RANDOMIZE_MEM_INIT vlsi_mem_gen (#572)	2017-03-07 01:56:15 -08:00
GuzTechandHenry Cook	8157cf1ede	Perform integer division when parsing rocketchip.DefaultConfig.conf (#493)	2017-01-13 16:40:02 -08:00
Colin SchmidtandAndrew Waterman	92718e4b61	fix null statement in vsli_mem_gen ala firrtl#264 (#252)	2016-09-07 11:04:36 -07:00
Megan Wachs	48098f5e2d	Bump FIRRTL to instantiate Sequential Memory Macros	2016-09-06 14:48:28 -07:00
Henry Cook	d3ccec1044	Massive update containing several months of changes from the now-defunct private chip repo. ... * Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules.	2015-07-02 14:43:30 -07:00
Schuyler Eldridge	b4cd8c5981	Fix vlsi_mem_gen for Python 2 or 3	2015-06-25 12:48:31 -07:00
Yunsup Lee	1cfd9f5a0e	add LICENSE	2014-09-12 10:15:04 -07:00
Yunsup Lee	ddfd3ce968	further generalize fpga/vlsi builds	2014-09-08 00:21:57 -07:00
Yunsup Lee	1cb2d1d7b7	initialize all SRAMs to avoid X propagation problem	2014-09-04 11:06:01 -07:00
Yunsup Lee	c03c09ec31	update for rocket-chip release	2014-08-31 20:26:55 -07:00