riscv/rocket-chip
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85 Commits

Author SHA1 Message Date
Wesley W. Terpstra
d6766a8c68 RocketTile: make sure 'hartid' is available for traits (#1037) 2017-10-09 21:03:18 -07:00
Andrew Waterman
2c4009a138 Fix paddrBits < xLen && paddrBits == vaddrBits case 
Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
 2017-10-09 16:48:04 -07:00
Andrew Waterman
986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits 
This supports addressing a >39-bit physical address space.
 2017-10-08 01:21:47 -07:00
Andrew Waterman
70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman
34e96c03b1 Move HCF to BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman
71205b70cc Make RocketTileWrapper a BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman
4645b61fd3 Decouple BaseTile from HasTileLinkMasterPort 2017-10-07 17:36:24 -07:00
Henry Styles
5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles
7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00
Henry Cook
8da7aabd51 tile: supply hartid from RocketTileParams 
make WithNCores partial configs override rather than append more tiles
 2017-10-05 00:31:53 -07:00
Andrew Waterman
7bcf28c585 Define fetchBytes in HasCoreParams, not Frontend 
It is more generally useful.
 2017-10-03 17:34:18 -07:00
Andrew Waterman
5cfe070932 Add option to make misa read-only 2017-10-03 17:34:18 -07:00
Andrew Waterman
09468a272b Add option to remove basic counters (mcycle/minstret) 2017-10-03 17:34:18 -07:00
Andrew Waterman
ab0821f25b Move microarchitecture-neutral params from Rocket to Core 
This makes some of the units more reusable.
 2017-10-03 17:34:18 -07:00
Wesley W. Terpstra
0268959c24 rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:02:04 -07:00
Wesley W. Terpstra
a27e853101 diplomacy: move rendering properties to edges 
FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
 2017-09-26 13:24:36 -07:00
Wesley W. Terpstra
60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs 2017-09-25 12:06:27 -07:00
Wesley W. Terpstra
b9a2e4c243 diplomacy: API beautification 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4 diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Wesley W. Terpstra
d89ee9d9d4 nodes: grab a name on construction 2017-09-22 14:38:47 -07:00
Henry Cook
e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook
28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Andrew Waterman
f1a506476b Merge pull request #994 from freechipsproject/beu 
Add L1 bus-error unit
 2017-09-20 12:17:08 -07:00
Andrew Waterman
afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman
4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Henry Cook
9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook
e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Wesley W. Terpstra
1365c5f90c diplomacy: implement DisableMonitors scope 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1a87ed1193 coreplex: add externalSlaveBuffers configuration option 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910 coreplex: rename externalBuffers to externalMasterBuffers 2017-09-07 16:03:35 -07:00
Henry Cook
3bde9506c6 coreplex: allow buffer chains on certain bus ports 2017-09-05 15:03:36 -07:00
Henry Cook
32cb358c81 coreplex: include optional tile name for downstream name stabilization 2017-08-30 15:48:55 -07:00
Shreesha Srinath
b1719cfee0 Fixing requirements for PAddrBits (#961) 
Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.
 2017-08-17 11:53:59 -07:00
Andrew Waterman
a3358f34a0 Fix priority inversion for two back-to-back divides (#948) 
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit.  While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
 2017-08-10 17:12:09 -07:00
Andrew Waterman
e140893a01 Use 1-entry queue on processor-side E-channel 
The cache can't sink a grant every cycle, so extra E buffering doesn't help.
 2017-07-31 18:06:54 -07:00
Yunsup Lee
f473e6bad0 tile: add optional boundary buffers 2017-07-31 15:57:22 -07:00
Wesley W. Terpstra
eadf4e9fcc Revert "tile: add option for tile boundary buffers" 
This reverts commit b64b87ad07.

The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
 2017-07-29 00:03:24 -07:00
Henry Cook
7eeb9dfd88 Merge pull request #899 from freechipsproject/wrapper-dedup 
Stabilize tile wrappers for downstream tools
 2017-07-28 10:52:59 -07:00
Henry Cook
b64b87ad07 tile: add option for tile boundary buffers 2017-07-27 17:30:51 -07:00
Henry Cook
266ed56e8d tile: turn off more slave port monitors 2017-07-27 15:28:53 -07:00
Andrew Waterman
15878d4691 Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
Henry Cook
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875) 
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
 2017-07-23 08:31:04 -07:00
Henry Cook
4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
 2017-07-07 10:48:16 -07:00
Andrew Waterman
90a7d6a343 Add L2 TLB option 2017-07-06 01:19:18 -07:00
Colin Schmidt
aced18b3bb Move RoCC interface to Diplomacy and TL2 (#807) 
* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
 2017-06-22 12:07:09 -07:00
Andrew Waterman
76af15a6ff Fix FPU control bug for div/sqrt 
I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
 2017-06-09 15:51:06 -07:00
Andrew Waterman
5a4daebbcc minNum -> minimumNumber (#766) 2017-06-08 11:12:52 -07:00
Andrew Waterman
8cb250cfe6 Fix FMUL sign, again (#789) 2017-06-08 01:50:00 -07:00
Andrew Waterman
07ad9203ff Fix FMUL sign of zero 2017-06-05 17:35:42 -07:00
Andrew Waterman
8229bdee03 Remove FP unboxing from FMA critical path 2017-06-02 20:44:52 -07:00