b7f1ba3428
tilelink: FIFOFixer must support null cases ( #860 )
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In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
2017-07-12 22:20:31 -07:00
0053a060ae
Merge pull request #859 from freechipsproject/fifo-fixer-configable
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Fifo fixer configable
2017-07-12 19:44:23 -07:00
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
09b9d33a9a
tilelink: FIFOFixer now has a policy parameter
2017-07-12 17:38:55 -07:00
b363a94480
diplomacy: add a new UNCACHEABLE RegionType
2017-07-12 16:31:50 -07:00
c8a7648169
diplomacy: only evaluate a Nexus node's map function once
2017-07-12 16:20:55 -07:00
af3976aa67
regmapper: add byte-sized RegField helper function ( #854 )
2017-07-10 21:08:02 -07:00
177ccbb663
regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was ( #855 )
2017-07-10 21:07:50 -07:00
287219da06
Merge pull request #851 from freechipsproject/chisel3clock
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Use chisel3 Clock() method.
2017-07-10 08:33:46 -07:00
29f5f77817
Merge pull request #853 from freechipsproject/sram-errors
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SRAM errors
2017-07-07 22:44:28 -07:00
5db0e770d5
tilelink: TestSRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
702143eb33
tilelink: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
9310a33e77
apb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
28fbf1af8e
ahb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:39 -07:00
df44b23956
axi4: SRAM can emulate incompletely populated memory
2017-07-07 21:40:39 -07:00
b2cc4b99ed
tilelink: TestSRAM reports errors on illegal access
2017-07-07 21:40:36 -07:00
e8cb6dafd3
tilelink: SRAM reports errors on illegal access
2017-07-07 21:15:36 -07:00
f1fb3be603
ahb: SRAM reports errors on illegal access
2017-07-07 21:15:36 -07:00
19851a7c9e
apb: SRAM reports errors on illegal access
2017-07-07 21:15:33 -07:00
025f7d890b
axi4: SRAM now reports errors on illegal address ( #852 )
2017-07-07 19:27:32 -07:00
2bf91a0558
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
c28c23150d
Merge pull request #850 from freechipsproject/plic_undefZero
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PLIC: (undefZero=true) Don't allow addresses to alias
2017-07-06 18:39:10 -07:00
76a1ae667f
PLIC: (undefZero=true) Don't allow addresses to alias
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While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
2017-07-06 17:57:08 -07:00
a0cbc376b4
Merge pull request #849 from freechipsproject/l2-tlb
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L1 memory system improvements
2017-07-06 13:03:06 -07:00
e1cc0a0a0e
Mask debug interrupts similarly to other interrupts ( #847 )
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This makes single-step exceptions higher-priority than debug interrupts.
2017-07-06 12:03:24 -07:00
b2351c5fbf
Use consistent casing
2017-07-06 11:16:56 -07:00
be4eceec0d
Fix stupid D$ probe bug
2017-07-06 01:20:47 -07:00
90a7d6a343
Add L2 TLB option
2017-07-06 01:19:18 -07:00
438abc76d2
Handle TL errors in L1 I$
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Cache the error bit in the tag array; report precisely on access.
2017-07-06 01:02:11 -07:00
988caf5e34
Merge pull request #848 from freechipsproject/revert-839-bump-firrtl
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Revert "Bump firrtl"
2017-07-05 22:32:45 -07:00
029886d0d5
Revert "Bump firrtl"
2017-07-05 21:13:47 -07:00
f6880555df
Merge pull request #839 from freechipsproject/bump-firrtl
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Bump firrtl
2017-07-05 14:59:58 -07:00
734a178e4e
Merge pull request #846 from freechipsproject/travis-delete-caches
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Update README_TRAVIS.md
2017-07-05 13:52:26 -07:00
94262ea950
Update README_TRAVIS.md
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add some headers
2017-07-05 11:45:04 -07:00
84c2bf5504
Update README_TRAVIS.md
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Clarify when to delete caches
2017-07-05 11:40:36 -07:00
bb4452435f
Bump Firrtl to get const prop registers and name improvements
2017-07-05 10:44:18 -07:00
ec9fbe26d8
Merge pull request #843 from freechipsproject/tag-ecc
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Add tag ECC to D$
2017-07-04 16:20:11 -07:00
0ef45fac9b
Add tag ECC to D$
2017-07-03 18:16:37 -07:00
e9752f76ae
Improve probe state machine
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- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
2017-07-03 16:25:04 -07:00
85f37146d5
Merge pull request #842 from freechipsproject/fesvr-multi
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Bump FESVR for multi-core support
2017-07-03 15:31:41 -07:00
ddd2b2236d
bump riscv-tools/riscv-fesvr to pick up multicore fixes
2017-07-03 13:25:05 -07:00
3d28c0182d
travis: add a branch whitelist with just 'master'.
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Travis allows us to build on branch updates and on PRs. Right now our process is to build always on PRs, but to manually only build 'master' when we know that riscv-tools has been bumped (because that rebuilds the master cache which holds riscv-tools). But this is an annoying and error-prone processes that requires extra admin permissions.
With this change, i think we can just leave "Build Branch Updates" to "ON" and get the same effect we are currently doing manually, because only on update to master branch will it do a build. PRs to master branch will get a build. PRs to other branches will I believe NOT get a build.
2017-07-03 13:25:05 -07:00
ee9789eb68
Merge pull request #840 from freechipsproject/fix-dcache-exception-assignment-order
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Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 18:50:49 -07:00
5b46350bc3
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 17:44:16 -07:00
69ab3626ca
Merge pull request #837 from freechipsproject/plic_recode
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plic: Recode to use OH knowledge
2017-06-30 16:05:32 -07:00
8c92c50d85
plic: make assertion comment right
2017-06-30 14:25:09 -07:00
f31ae008f3
plic: Clean up comments and simplify checking
2017-06-30 14:15:26 -07:00
76f8de75e3
plic: comment tidying
2017-06-30 12:51:09 -07:00
3da26b0aa8
plic: Add some assertions to check one-hot assumptions
2017-06-30 12:32:58 -07:00
