riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity
672 Commits 1 Branch 0 Tags 13 MiB
Commit Graph

10 Commits

Author SHA1 Message Date
Palmer Dabbelt 7c0c48fac4 Resurrect the backup memory port 
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
 2016-02-27 10:46:56 -08:00
Howard Mao bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Yunsup Lee 0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao 9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Howard Mao 4346111d2a fix remaining vsim harness typo 2015-10-19 20:20:14 -07:00
Henry Cook d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. 
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
 2015-07-02 14:43:30 -07:00
Yunsup Lee 1cfd9f5a0e add LICENSE 2014-09-12 10:15:04 -07:00
Yunsup Lee 02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Yunsup Lee c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00