590 lines
15 KiB
Verilog
590 lines
15 KiB
Verilog
// See LICENSE for license details.
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extern "A" void htif_init
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(
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input reg [31:0] htif_width,
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input reg [31:0] mem_width
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);
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extern "A" void htif_fini(input reg failure);
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extern "A" void htif_tick
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(
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output reg htif_in_valid,
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input reg htif_in_ready,
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output reg [`HTIF_WIDTH-1:0] htif_in_bits,
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input reg htif_out_valid,
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output reg htif_out_ready,
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input reg [`HTIF_WIDTH-1:0] htif_out_bits,
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output reg [31:0] exit
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);
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extern "A" void memory_tick
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(
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input reg ar_valid,
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output reg ar_ready,
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input reg [`MEM_ADDR_BITS-1:0] ar_addr,
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input reg [`MEM_ID_BITS-1:0] ar_id,
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input reg [2:0] ar_size,
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input reg [7:0] ar_len,
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input reg aw_valid,
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output reg aw_ready,
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input reg [`MEM_ADDR_BITS-1:0] aw_addr,
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input reg [`MEM_ID_BITS-1:0] aw_id,
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input reg [2:0] aw_size,
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input reg [7:0] aw_len,
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input reg w_valid,
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output reg w_ready,
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input reg [`MEM_STRB_BITS-1:0] w_strb,
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input reg [`MEM_DATA_BITS-1:0] w_data,
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input reg w_last,
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output reg r_valid,
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input reg r_ready,
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output reg [1:0] r_resp,
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output reg [`MEM_ID_BITS-1:0] r_id,
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output reg [`MEM_DATA_BITS-1:0] r_data,
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output reg r_last,
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output reg b_valid,
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input reg b_ready,
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output reg [1:0] b_resp,
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output reg [`MEM_ID_BITS-1:0] b_id
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);
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module rocketTestHarness;
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reg [31:0] seed;
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initial seed = $get_initial_random_seed();
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//-----------------------------------------------
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// Instantiate the processor
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reg clk = 1'b0;
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reg reset = 1'b1;
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reg r_reset;
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reg start = 1'b0;
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always #`CLOCK_PERIOD clk = ~clk;
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wire ar_valid;
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reg ar_ready;
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wire [`MEM_ADDR_BITS-1:0] ar_addr;
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wire [`MEM_ID_BITS-1:0] ar_id;
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wire [2:0] ar_size;
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wire [7:0] ar_len;
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wire aw_valid;
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reg aw_ready;
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wire [`MEM_ADDR_BITS-1:0] aw_addr;
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wire [`MEM_ID_BITS-1:0] aw_id;
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wire [2:0] aw_size;
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wire [7:0] aw_len;
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wire w_valid;
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reg w_ready;
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wire [`MEM_STRB_BITS-1:0] w_strb;
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wire [`MEM_DATA_BITS-1:0] w_data;
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wire w_last;
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reg r_valid;
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wire r_ready;
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reg [1:0] r_resp;
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reg [`MEM_ID_BITS-1:0] r_id;
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reg [`MEM_DATA_BITS-1:0] r_data;
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reg r_last;
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reg b_valid;
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wire b_ready;
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reg [1:0] b_resp;
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reg [`MEM_ID_BITS-1:0] b_id;
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reg htif_out_ready;
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wire htif_in_valid;
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wire [`HTIF_WIDTH-1:0] htif_in_bits;
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wire htif_in_ready, htif_out_valid;
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wire [`HTIF_WIDTH-1:0] htif_out_bits;
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wire htif_out_stats;
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wire mem_bk_in_valid;
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wire mem_bk_out_valid;
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wire mem_bk_out_ready;
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wire [`HTIF_WIDTH-1:0] mem_in_bits;
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wire htif_clk;
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wire #0.1 htif_in_valid_delay = htif_in_valid;
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wire htif_in_ready_delay; assign #0.1 htif_in_ready = htif_in_ready_delay;
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wire [`HTIF_WIDTH-1:0] #0.1 htif_in_bits_delay = htif_in_bits;
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wire htif_out_valid_delay; assign #0.1 htif_out_valid = htif_out_valid_delay;
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wire #0.1 htif_out_ready_delay = htif_out_ready;
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wire [`HTIF_WIDTH-1:0] htif_out_bits_delay; assign #0.1 htif_out_bits = htif_out_bits_delay;
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wire htif_out_stats_delay; assign #0.1 htif_out_stats = htif_out_stats_delay;
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wire ar_valid_delay; assign #0.1 ar_valid = ar_valid_delay;
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wire #0.1 ar_ready_delay = ar_ready;
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wire [`MEM_ADDR_BITS-1:0] ar_addr_delay; assign #0.1 ar_addr = ar_addr_delay;
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wire [`MEM_ID_BITS-1:0] ar_id_delay; assign #0.1 ar_id = ar_id_delay;
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wire [2:0] ar_size_delay; assign #0.1 ar_size = ar_size_delay;
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wire [7:0] ar_len_delay; assign #0.1 ar_len = ar_len_delay;
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wire aw_valid_delay; assign #0.1 aw_valid = aw_valid_delay;
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wire #0.1 aw_ready_delay = aw_ready;
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wire [`MEM_ADDR_BITS-1:0] aw_addr_delay; assign #0.1 aw_addr = aw_addr_delay;
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wire [`MEM_ID_BITS-1:0] aw_id_delay; assign #0.1 aw_id = aw_id_delay;
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wire [2:0] aw_size_delay; assign #0.1 aw_size = aw_size_delay;
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wire [7:0] aw_len_delay; assign #0.1 aw_len = aw_len_delay;
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wire w_valid_delay; assign #0.1 w_valid = w_valid_delay;
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wire #0.1 w_ready_delay = w_ready;
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wire [`MEM_STRB_BITS-1:0] w_strb_delay; assign #0.1 w_strb = w_strb_delay;
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wire [`MEM_DATA_BITS-1:0] w_data_delay; assign #0.1 w_data = w_data_delay;
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wire w_last_delay; assign #0.1 w_last = w_last_delay;
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wire #0.1 r_valid_delay = r_valid;
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wire r_ready_delay; assign #0.1 r_ready = r_ready_delay;
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wire [1:0] #0.1 r_resp_delay = r_resp;
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wire [`MEM_ID_BITS-1:0] #0.1 r_id_delay = r_id;
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wire [`MEM_DATA_BITS-1:0] #0.1 r_data_delay = r_data;
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wire #0.1 r_last_delay = r_last;
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wire #0.1 b_valid_delay = b_valid;
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wire b_ready_delay; assign #0.1 b_ready = b_ready_delay;
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wire [1:0] #0.1 b_resp_delay = b_resp;
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wire [`MEM_ID_BITS-1:0] #0.1 b_id_delay = b_id;
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wire #0.1 mem_bk_out_ready_delay = mem_bk_out_ready;
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wire #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
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wire mem_bk_out_valid_delay; assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
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`ifdef FPGA
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assign mem_bk_out_valid_delay = 1'b0;
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assign htif_out_stats_delay = 1'b0;
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`endif
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Top dut
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(
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.clk(clk),
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.reset(reset),
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.io_host_in_valid(htif_in_valid_delay),
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.io_host_in_ready(htif_in_ready_delay),
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.io_host_in_bits(htif_in_bits_delay),
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.io_host_out_valid(htif_out_valid_delay),
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.io_host_out_ready(htif_out_ready_delay),
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.io_host_out_bits(htif_out_bits_delay),
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`ifndef FPGA
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.io_host_clk(htif_clk),
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.io_host_clk_edge(),
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.io_host_debug_stats_csr(htif_out_stats_delay),
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`ifdef MEM_BACKUP_EN
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.io_mem_backup_ctrl_en(1'b1),
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`else
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.io_mem_backup_ctrl_en(1'b0),
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`endif // MEM_BACKUP_EN
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.io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay),
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.io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay),
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.io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay),
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`else
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.io_host_clk (),
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.io_host_clk_edge (),
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.io_host_debug_stats_csr (),
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.io_mem_backup_ctrl_en (1'b0),
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.io_mem_backup_ctrl_in_valid (1'b0),
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.io_mem_backup_ctrl_out_ready (1'b0),
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.io_mem_backup_ctrl_out_valid (),
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`endif // FPGA
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.io_mem_ar_valid (ar_valid_delay),
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.io_mem_ar_ready (ar_ready_delay),
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.io_mem_ar_bits_addr (ar_addr_delay),
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.io_mem_ar_bits_id (ar_id_delay),
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.io_mem_ar_bits_size (ar_size_delay),
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.io_mem_ar_bits_len (ar_len_delay),
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.io_mem_ar_bits_burst (),
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.io_mem_ar_bits_lock (),
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.io_mem_ar_bits_cache (),
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.io_mem_ar_bits_prot (),
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.io_mem_ar_bits_qos (),
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.io_mem_ar_bits_region (),
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.io_mem_ar_bits_user (),
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.io_mem_aw_valid (aw_valid_delay),
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.io_mem_aw_ready (aw_ready_delay),
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.io_mem_aw_bits_addr (aw_addr_delay),
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.io_mem_aw_bits_id (aw_id_delay),
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.io_mem_aw_bits_size (aw_size_delay),
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.io_mem_aw_bits_len (aw_len_delay),
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.io_mem_aw_bits_burst (),
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.io_mem_aw_bits_lock (),
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.io_mem_aw_bits_cache (),
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.io_mem_aw_bits_prot (),
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.io_mem_aw_bits_qos (),
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.io_mem_aw_bits_region (),
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.io_mem_aw_bits_user (),
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.io_mem_w_valid (w_valid_delay),
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.io_mem_w_ready (w_ready_delay),
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.io_mem_w_bits_strb (w_strb_delay),
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.io_mem_w_bits_data (w_data_delay),
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.io_mem_w_bits_last (w_last_delay),
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.io_mem_w_bits_user (),
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.io_mem_r_valid (r_valid_delay),
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.io_mem_r_ready (r_ready_delay),
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.io_mem_r_bits_resp (r_resp_delay),
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.io_mem_r_bits_id (r_id_delay),
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.io_mem_r_bits_data (r_data_delay),
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.io_mem_r_bits_last (r_last_delay),
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.io_mem_r_bits_user (1'b0),
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.io_mem_b_valid (b_valid_delay),
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.io_mem_b_ready (b_ready_delay),
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.io_mem_b_bits_resp (b_resp_delay),
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.io_mem_b_bits_id (b_id_delay),
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.io_mem_b_bits_user (1'b0)
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);
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`ifdef FPGA
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assign htif_clk = clk;
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`endif
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//-----------------------------------------------
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// Memory interface
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always @(negedge clk)
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begin
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r_reset <= reset;
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if (reset || r_reset)
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begin
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ar_ready <= 1'b0;
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aw_ready <= 1'b0;
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w_ready <= 1'b0;
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r_valid <= 1'b0;
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r_resp <= 2'b0;
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r_id <= {`MEM_ID_BITS {1'b0}};
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r_data <= {`MEM_DATA_BITS {1'b0}};
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r_last <= 1'b0;
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b_valid <= 1'b0;
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b_resp <= 2'b0;
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b_id <= {`MEM_ID_BITS {1'b0}};
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end
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else
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begin
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memory_tick
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(
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ar_valid,
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ar_ready,
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ar_addr,
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ar_id,
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ar_size,
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ar_len,
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aw_valid,
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aw_ready,
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aw_addr,
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aw_id,
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aw_size,
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aw_len,
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w_valid,
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w_ready,
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w_strb,
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w_data,
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w_last,
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r_valid,
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r_ready,
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r_resp,
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r_id,
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r_data,
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r_last,
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b_valid,
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b_ready,
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b_resp,
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b_id
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);
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end
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end
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wire mem_bk_req_valid, mem_bk_req_rw, mem_bk_req_data_valid;
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wire [`MEM_ID_BITS-1:0] mem_bk_req_tag;
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wire [`MEM_ADDR_BITS-1:0] mem_bk_req_addr;
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wire [`MEM_DATA_BITS-1:0] mem_bk_req_data_bits;
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wire mem_bk_req_ready, mem_bk_req_data_ready, mem_bk_resp_valid;
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wire [`MEM_ID_BITS-1:0] mem_bk_resp_tag;
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wire [`MEM_DATA_BITS-1:0] mem_bk_resp_data;
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`ifdef MEM_BACKUP_EN
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memdessertMemDessert dessert
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(
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.clk(htif_clk),
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.reset(reset),
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.io_narrow_req_valid(mem_bk_out_valid),
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.io_narrow_req_ready(mem_bk_out_ready),
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.io_narrow_req_bits(htif_out_bits),
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.io_narrow_resp_valid(mem_bk_in_valid),
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.io_narrow_resp_bits(mem_in_bits),
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.io_wide_req_cmd_valid(mem_bk_req_valid),
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.io_wide_req_cmd_ready(mem_bk_req_ready),
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.io_wide_req_cmd_bits_rw(mem_bk_req_rw),
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.io_wide_req_cmd_bits_addr(mem_bk_req_addr),
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.io_wide_req_cmd_bits_tag(mem_bk_req_tag),
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.io_wide_req_data_valid(mem_bk_req_data_valid),
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.io_wide_req_data_ready(mem_bk_req_data_ready),
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.io_wide_req_data_bits_data(mem_bk_req_data_bits),
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.io_wide_resp_valid(mem_bk_resp_valid),
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.io_wide_resp_ready(),
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.io_wide_resp_bits_data(mem_bk_resp_data),
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.io_wide_resp_bits_tag(mem_bk_resp_tag)
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);
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BackupMemory mem
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(
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.clk(htif_clk),
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.reset(reset),
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.mem_req_valid(mem_bk_req_valid),
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.mem_req_ready(mem_bk_req_ready),
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.mem_req_rw(mem_bk_req_rw),
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.mem_req_addr(mem_bk_req_addr),
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.mem_req_tag(mem_bk_req_tag),
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.mem_req_data_valid(mem_bk_req_data_valid),
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.mem_req_data_ready(mem_bk_req_data_ready),
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.mem_req_data_bits(mem_bk_req_data_bits),
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.mem_resp_valid(mem_bk_resp_valid),
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.mem_resp_data(mem_bk_resp_data),
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.mem_resp_tag(mem_bk_resp_tag)
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);
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`else
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// set dessert outputs to zero when !backupmem_en
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assign mem_bk_out_ready = 1'b0;
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assign mem_bk_in_valid = 1'b0;
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assign mem_in_bits = {`HTIF_WIDTH {1'b0}};
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assign mem_bk_req_valid = 1'b0;
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assign mem_bk_req_ready = 1'b0;
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assign mem_bk_req_addr = {`MEM_ADDR_BITS {1'b0}};
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assign mem_bk_req_rw = 1'b0;
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assign mem_bk_req_tag = {`MEM_ID_BITS {1'b0}};
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assign mem_bk_req_data_valid = 1'b0;
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assign mem_bk_req_data_bits = 16'd0;
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`endif
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reg htif_in_valid_premux;
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reg [`HTIF_WIDTH-1:0] htif_in_bits_premux;
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assign htif_in_bits = mem_bk_in_valid ? mem_in_bits : htif_in_bits_premux;
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assign htif_in_valid = htif_in_valid_premux && !mem_bk_in_valid;
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wire htif_in_ready_premux = htif_in_ready && !mem_bk_in_valid;
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reg [31:0] exit = 0;
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always @(posedge htif_clk)
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begin
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if (reset || r_reset)
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begin
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htif_in_valid_premux <= 0;
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htif_out_ready <= 0;
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exit <= 0;
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end
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else
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begin
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htif_tick
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(
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htif_in_valid_premux,
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htif_in_ready_premux,
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htif_in_bits_premux,
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htif_out_valid,
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htif_out_ready,
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htif_out_bits,
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exit
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);
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end
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end
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//-----------------------------------------------
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// Start the simulation
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reg [ 31:0] htif_width = `HTIF_WIDTH;
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reg [ 31:0] mem_width = `MEM_DATA_BITS;
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reg [ 63:0] max_cycles = 0;
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reg [ 63:0] trace_count = 0;
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reg [1023:0] loadmem = 0;
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reg [1023:0] vcdplusfile = 0;
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reg [1023:0] vcdfile = 0;
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reg stats_active = 0;
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reg stats_tracking = 0;
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reg verbose = 0;
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integer stderr = 32'h80000002;
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// Some helper functions for turning on, stopping, and finishing stat tracking
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task start_stats;
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begin
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if(!reset || !stats_active)
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begin
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`ifdef DEBUG
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if(vcdplusfile)
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begin
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$vcdpluson(0);
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$vcdplusmemon(0);
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end
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if(vcdfile)
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begin
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$dumpon;
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end
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`endif
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assign stats_tracking = 1;
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end
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end
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endtask
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task stop_stats;
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begin
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`ifdef DEBUG
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$vcdplusoff; $dumpoff;
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`endif
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assign stats_tracking = 0;
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end
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endtask
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`ifdef DEBUG
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`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
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`else
|
|
`define VCDPLUSCLOSE
|
|
`endif
|
|
|
|
// Read input arguments and initialize
|
|
initial
|
|
begin
|
|
$value$plusargs("max-cycles=%d", max_cycles);
|
|
`ifdef MEM_BACKUP_EN
|
|
$value$plusargs("loadmem=%s", loadmem);
|
|
if (loadmem)
|
|
$readmemh(loadmem, mem.ram);
|
|
`endif
|
|
verbose = $test$plusargs("verbose");
|
|
htif_init(htif_width, mem_width);
|
|
`ifdef DEBUG
|
|
stats_active = $test$plusargs("stats");
|
|
if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
|
|
begin
|
|
$vcdplusfile(vcdplusfile);
|
|
end
|
|
if ($value$plusargs("vcdfile=%s", vcdfile))
|
|
begin
|
|
$dumpfile(vcdfile);
|
|
$dumpvars(0, dut);
|
|
end
|
|
if (!stats_active)
|
|
begin
|
|
start_stats;
|
|
end
|
|
else
|
|
begin
|
|
if(vcdfile)
|
|
begin
|
|
$dumpoff;
|
|
end
|
|
end
|
|
`endif
|
|
|
|
// Strobe reset
|
|
#777.7 reset = 0;
|
|
|
|
end
|
|
|
|
reg [255:0] reason = 0;
|
|
always @(posedge clk)
|
|
begin
|
|
if (max_cycles > 0 && trace_count > max_cycles)
|
|
reason = "timeout";
|
|
if (exit > 1)
|
|
$sformat(reason, "tohost = %d", exit >> 1);
|
|
|
|
if (reason)
|
|
begin
|
|
$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
|
|
`VCDPLUSCLOSE
|
|
htif_fini(1'b1);
|
|
end
|
|
|
|
if (exit == 1)
|
|
begin
|
|
`VCDPLUSCLOSE
|
|
htif_fini(1'b0);
|
|
end
|
|
end
|
|
|
|
//-----------------------------------------------
|
|
// Tracing code
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if(stats_active)
|
|
begin
|
|
if(!stats_tracking && htif_out_stats)
|
|
begin
|
|
start_stats;
|
|
end
|
|
if(stats_tracking && !htif_out_stats)
|
|
begin
|
|
stop_stats;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge htif_clk)
|
|
begin
|
|
if (verbose && mem_bk_req_valid && mem_bk_req_ready)
|
|
begin
|
|
$fdisplay(stderr, "MB: rw=%d addr=%x", mem_bk_req_rw, {mem_bk_req_addr,6'd0});
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (verbose)
|
|
begin
|
|
if (ar_valid && ar_ready)
|
|
begin
|
|
$fdisplay(stderr, "MC: ar addr=%x", ar_addr);
|
|
end
|
|
if (aw_valid && aw_ready)
|
|
begin
|
|
$fdisplay(stderr, "MC: aw addr=%x", aw_addr);
|
|
end
|
|
if (w_valid && w_ready)
|
|
begin
|
|
$fdisplay(stderr, "MC: w data=%x", w_data);
|
|
end
|
|
if (r_valid && r_ready)
|
|
begin
|
|
$fdisplay(stderr, "MC: r data=%x", r_data);
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
trace_count = trace_count + 1;
|
|
`ifdef GATE_LEVEL
|
|
if (verbose)
|
|
begin
|
|
$fdisplay(stderr, "C: %10d", trace_count-1);
|
|
end
|
|
`endif
|
|
end
|
|
|
|
endmodule
|