451 lines
12 KiB
Verilog
451 lines
12 KiB
Verilog
// See LICENSE for license details.
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extern "A" void htif_init
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(
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input reg [31:0] htif_width,
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input reg [31:0] mem_width
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);
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extern "A" void htif_fini(input reg failure);
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extern "A" void htif_tick
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(
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output reg htif_in_valid,
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input reg htif_in_ready,
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output reg [`HTIF_WIDTH-1:0] htif_in_bits,
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input reg htif_out_valid,
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output reg htif_out_ready,
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input reg [`HTIF_WIDTH-1:0] htif_out_bits,
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output reg [31:0] exit
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);
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extern "A" void memory_tick
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(
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input reg mem_req_valid,
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output reg mem_req_ready,
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input reg mem_req_store,
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input reg [`MEM_ADDR_BITS-1:0] mem_req_bits_addr,
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input reg [`MEM_TAG_BITS-1:0] mem_req_bits_tag,
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input reg mem_req_data_valid,
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output reg mem_req_data_ready,
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input reg [`MEM_DATA_BITS-1:0] mem_req_data_bits,
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output reg mem_resp_valid,
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input reg mem_resp_ready,
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output reg [`MEM_TAG_BITS-1:0] mem_resp_bits_tag,
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output reg [`MEM_DATA_BITS-1:0] mem_resp_bits_data
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);
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module rocketTestHarness;
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reg [31:0] seed;
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initial seed = $get_initial_random_seed();
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//-----------------------------------------------
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// Instantiate the processor
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reg clk = 0;
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reg reset = 1;
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reg r_reset;
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reg start = 0;
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always #`CLOCK_PERIOD clk = ~clk;
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wire mem_req_valid;
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reg mem_req_ready;
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wire mem_req_bits_rw;
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wire [`MEM_ADDR_BITS-1:0] mem_req_bits_addr;
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wire [`MEM_TAG_BITS-1:0] mem_req_bits_tag;
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wire mem_req_data_valid;
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reg mem_req_data_ready;
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wire [`MEM_DATA_BITS-1:0] mem_req_data_bits;
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reg mem_resp_valid;
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wire mem_resp_ready;
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reg [`MEM_TAG_BITS-1:0] mem_resp_bits_tag;
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reg [`MEM_DATA_BITS-1:0] mem_resp_bits_data;
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reg htif_out_ready;
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wire htif_in_valid;
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wire [`HTIF_WIDTH-1:0] htif_in_bits;
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wire htif_in_ready, htif_out_valid;
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wire [`HTIF_WIDTH-1:0] htif_out_bits;
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wire mem_bk_in_valid;
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wire mem_bk_out_valid;
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wire mem_bk_out_ready;
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wire [`HTIF_WIDTH-1:0] mem_in_bits;
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wire htif_clk;
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wire #0.1 htif_in_valid_delay = htif_in_valid;
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wire htif_in_ready_delay; assign #0.1 htif_in_ready = htif_in_ready_delay;
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wire [`HTIF_WIDTH-1:0] #0.1 htif_in_bits_delay = htif_in_bits;
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wire htif_out_valid_delay; assign #0.1 htif_out_valid = htif_out_valid_delay;
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wire #0.1 htif_out_ready_delay = htif_out_ready;
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wire [`HTIF_WIDTH-1:0] htif_out_bits_delay; assign #0.1 htif_out_bits = htif_out_bits_delay;
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wire htif_out_stats_delay; assign #0.1 htif_out_stats = htif_out_stats_delay;
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wire mem_req_valid_delay; assign #0.1 mem_req_valid = mem_req_valid_delay;
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wire #0.1 mem_req_ready_delay = mem_req_ready;
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wire [`MEM_TAG_BITS-1:0] mem_req_bits_tag_delay; assign #0.1 mem_req_bits_tag = mem_req_bits_tag_delay;
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wire [`MEM_ADDR_BITS-1:0] mem_req_bits_addr_delay; assign #0.1 mem_req_bits_addr = mem_req_bits_addr_delay;
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wire mem_req_bits_rw_delay; assign #0.1 mem_req_bits_rw = mem_req_bits_rw_delay;
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wire mem_req_data_valid_delay; assign #0.1 mem_req_data_valid = mem_req_data_valid_delay;
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wire #0.1 mem_req_data_ready_delay = mem_req_data_ready;
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wire [`MEM_DATA_BITS-1:0] mem_req_data_bits_delay; assign #0.1 mem_req_data_bits = mem_req_data_bits_delay;
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wire #0.1 mem_resp_valid_delay = mem_resp_valid;
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wire mem_resp_ready_delay; assign #0.1 mem_resp_ready = mem_resp_ready_delay;
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wire [`MEM_TAG_BITS-1:0] #0.1 mem_resp_bits_tag_delay = mem_resp_bits_tag;
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wire [`MEM_DATA_BITS-1:0] #0.1 mem_resp_bits_data_delay = mem_resp_bits_data;
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wire #0.1 mem_bk_out_ready_delay = mem_bk_out_ready;
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wire #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
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wire mem_bk_out_valid_delay; assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;
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Top dut
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(
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.clk(clk),
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.reset(reset),
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.io_host_in_valid(htif_in_valid_delay),
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.io_host_in_ready(htif_in_ready_delay),
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.io_host_in_bits(htif_in_bits_delay),
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.io_host_out_valid(htif_out_valid_delay),
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.io_host_out_ready(htif_out_ready_delay),
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.io_host_out_bits(htif_out_bits_delay),
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`ifndef FPGA
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.io_host_clk(htif_clk),
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.io_host_clk_edge(),
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.io_host_debug_stats_pcr(htif_out_stats_delay),
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`ifdef MEM_BACKUP_EN
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.io_mem_backup_ctrl_en(1'b1),
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`else
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.io_mem_backup_ctrl_en(1'b0),
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`endif
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.io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay),
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.io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay),
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.io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay),
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`endif
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.io_mem_req_cmd_valid(mem_req_valid_delay),
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.io_mem_req_cmd_ready(mem_req_ready_delay),
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.io_mem_req_cmd_bits_rw(mem_req_bits_rw_delay),
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.io_mem_req_cmd_bits_addr(mem_req_bits_addr_delay),
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.io_mem_req_cmd_bits_tag(mem_req_bits_tag_delay),
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.io_mem_req_data_valid(mem_req_data_valid_delay),
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.io_mem_req_data_ready(mem_req_data_ready_delay),
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.io_mem_req_data_bits_data(mem_req_data_bits_delay),
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.io_mem_resp_valid(mem_resp_valid_delay),
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.io_mem_resp_ready(mem_resp_ready_delay),
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.io_mem_resp_bits_tag(mem_resp_bits_tag_delay),
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.io_mem_resp_bits_data(mem_resp_bits_data_delay)
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);
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`ifdef FPGA
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assign htif_clk = clk;
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`endif
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//-----------------------------------------------
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// Memory interface
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always @(negedge clk)
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begin
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r_reset <= reset;
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if (reset || r_reset)
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begin
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mem_req_ready <= 0;
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mem_req_data_ready <= 0;
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mem_resp_valid <= 0;
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mem_resp_bits_tag <= 0;
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mem_resp_bits_data <= 0;
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end
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else
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begin
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memory_tick
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(
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mem_req_valid,
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mem_req_ready,
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mem_req_bits_rw,
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mem_req_bits_addr,
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mem_req_bits_tag,
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mem_req_data_valid,
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mem_req_data_ready,
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mem_req_data_bits,
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mem_resp_valid,
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mem_resp_ready,
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mem_resp_bits_tag,
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mem_resp_bits_data
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);
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end
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end
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wire mem_bk_req_valid, mem_bk_req_rw, mem_bk_req_data_valid;
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wire [`MEM_TAG_BITS-1:0] mem_bk_req_tag;
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wire [`MEM_ADDR_BITS-1:0] mem_bk_req_addr;
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wire [`MEM_DATA_BITS-1:0] mem_bk_req_data_bits;
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wire mem_bk_req_ready, mem_bk_req_data_ready, mem_bk_resp_valid;
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wire [`MEM_TAG_BITS-1:0] mem_bk_resp_tag;
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wire [`MEM_DATA_BITS-1:0] mem_bk_resp_data;
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`ifdef MEM_BACKUP_EN
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memdessertMemDessert dessert
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(
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.clk(htif_clk),
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.reset(reset),
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.io_narrow_req_valid(mem_bk_out_valid),
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.io_narrow_req_ready(mem_bk_out_ready),
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.io_narrow_req_bits(htif_out_bits),
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.io_narrow_resp_valid(mem_bk_in_valid),
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.io_narrow_resp_bits(mem_in_bits),
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.io_wide_req_cmd_valid(mem_bk_req_valid),
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.io_wide_req_cmd_ready(mem_bk_req_ready),
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.io_wide_req_cmd_bits_rw(mem_bk_req_rw),
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.io_wide_req_cmd_bits_addr(mem_bk_req_addr),
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.io_wide_req_cmd_bits_tag(mem_bk_req_tag),
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.io_wide_req_data_valid(mem_bk_req_data_valid),
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.io_wide_req_data_ready(mem_bk_req_data_ready),
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.io_wide_req_data_bits_data(mem_bk_req_data_bits),
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.io_wide_resp_valid(mem_bk_resp_valid),
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.io_wide_resp_ready(),
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.io_wide_resp_bits_data(mem_bk_resp_data),
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.io_wide_resp_bits_tag(mem_bk_resp_tag)
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);
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BackupMemory mem
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(
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.clk(htif_clk),
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.reset(reset),
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.mem_req_valid(mem_bk_req_valid),
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.mem_req_ready(mem_bk_req_ready),
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.mem_req_rw(mem_bk_req_rw),
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.mem_req_addr(mem_bk_req_addr),
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.mem_req_tag(mem_bk_req_tag),
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.mem_req_data_valid(mem_bk_req_data_valid),
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.mem_req_data_ready(mem_bk_req_data_ready),
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.mem_req_data_bits(mem_bk_req_data_bits),
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.mem_resp_valid(mem_bk_resp_valid),
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.mem_resp_data(mem_bk_resp_data),
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.mem_resp_tag(mem_bk_resp_tag)
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);
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`else
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// set dessert outputs to zero when !backupmem_en
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assign mem_bk_out_ready = 0;
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assign mem_bk_in_valid = 0;
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assign mem_in_bits = 0;
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assign mem_bk_req_valid = 0;
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assign mem_bk_req_addr = 0;
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assign mem_bk_req_rw = 0;
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assign mem_bk_req_tag = 0;
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assign mem_bk_req_data_valid = 0;
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assign mem_bk_req_data_bits = 0;
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`endif
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reg htif_in_valid_premux;
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reg [`HTIF_WIDTH-1:0] htif_in_bits_premux;
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assign htif_in_bits = mem_bk_in_valid ? mem_in_bits : htif_in_bits_premux;
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assign htif_in_valid = htif_in_valid_premux && !mem_bk_in_valid;
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wire htif_in_ready_premux = htif_in_ready && !mem_bk_in_valid;
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reg [31:0] exit = 0;
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always @(posedge htif_clk)
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begin
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if (reset || r_reset)
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begin
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htif_in_valid_premux <= 0;
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htif_out_ready <= 0;
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exit <= 0;
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end
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else
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begin
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htif_tick
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(
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htif_in_valid_premux,
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htif_in_ready_premux,
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htif_in_bits_premux,
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htif_out_valid,
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htif_out_ready,
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htif_out_bits,
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exit
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);
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end
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end
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//-----------------------------------------------
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// Start the simulation
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reg [ 31:0] htif_width = `HTIF_WIDTH;
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reg [ 31:0] mem_width = `MEM_DATA_BITS;
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reg [ 63:0] max_cycles = 0;
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reg [ 63:0] trace_count = 0;
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reg [1023:0] loadmem = 0;
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reg [1023:0] vcdplusfile = 0;
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reg [1023:0] vcdfile = 0;
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reg stats_active = 0;
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reg stats_tracking = 0;
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reg verbose = 0;
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integer stderr = 32'h80000002;
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// Some helper functions for turning on, stopping, and finishing stat tracking
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task start_stats;
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begin
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if(!reset || !stats_active)
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begin
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`ifdef DEBUG
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if(vcdplusfile)
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begin
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$vcdpluson(0);
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$vcdplusmemon(0);
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end
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if(vcdfile)
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begin
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$dumpon;
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end
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`endif
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assign stats_tracking = 1;
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end
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end
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endtask
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task stop_stats;
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begin
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`ifdef DEBUG
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$vcdplusoff; $dumpoff;
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`endif
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assign stats_tracking = 0;
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end
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endtask
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`ifdef DEBUG
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`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
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`else
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`define VCDPLUSCLOSE
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`endif
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// Read input arguments and initialize
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initial
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begin
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$value$plusargs("max-cycles=%d", max_cycles);
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`ifdef MEM_BACKUP_EN
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$value$plusargs("loadmem=%s", loadmem);
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if (loadmem)
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$readmemh(loadmem, mem.ram);
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`endif
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verbose = $test$plusargs("verbose");
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htif_init(htif_width, mem_width);
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`ifdef DEBUG
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stats_active = $test$plusargs("stats");
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if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
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begin
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$vcdplusfile(vcdplusfile);
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end
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if ($value$plusargs("vcdfile=%s", vcdfile))
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begin
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$dumpfile(vcdfile);
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$dumpvars(0, dut);
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end
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if (!stats_active)
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begin
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start_stats;
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end
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else
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begin
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if(vcdfile)
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begin
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$dumpoff;
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end
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end
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`endif
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// Strobe reset
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#777.7 reset = 0;
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end
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reg [255:0] reason = 0;
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always @(posedge clk)
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begin
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if (max_cycles > 0 && trace_count > max_cycles)
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reason = "timeout";
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if (exit > 1)
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$sformat(reason, "tohost = %d", exit >> 1);
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if (reason)
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begin
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$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
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`VCDPLUSCLOSE
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htif_fini(1);
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end
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if (exit == 1)
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begin
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`VCDPLUSCLOSE
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htif_fini(0);
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end
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end
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//-----------------------------------------------
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// Tracing code
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always @(posedge clk)
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begin
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if(stats_active)
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begin
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if(!stats_tracking && htif_out_stats)
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begin
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start_stats;
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end
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if(stats_tracking && !htif_out_stats)
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begin
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stop_stats;
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end
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end
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end
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always @(posedge htif_clk)
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begin
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if (verbose && mem_bk_req_valid && mem_bk_req_ready)
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begin
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$fdisplay(stderr, "MB: rw=%d addr=%x", mem_bk_req_rw, {mem_bk_req_addr,6'd0});
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end
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end
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always @(posedge clk)
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begin
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if (verbose && mem_req_valid && mem_req_ready)
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begin
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$fdisplay(stderr, "MC: rw=%d addr=%x", mem_req_bits_rw, {mem_req_bits_addr,6'd0});
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end
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end
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always @(posedge clk)
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begin
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trace_count = trace_count + 1;
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`ifdef GATE_LEVEL
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if (verbose)
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begin
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$fdisplay(stderr, "C: %10d", trace_count-1);
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end
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`endif
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end
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endmodule
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