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Commit Graph

24 Commits

Author SHA1 Message Date
7a1d107c9e rocketchip: include an ErrorSlave by default 2017-05-01 22:53:37 -07:00
d67738204f Interrupts: Less Pessimistic Synchronization (#714)
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
a3e56cfa5e rocketchip: add Zero device to the memory subsystem 2017-02-03 17:19:24 -08:00
e22b01a6fa jtag_dtm: Update regression to run and pass. 2017-01-18 12:08:13 -08:00
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
13190a5de0 rocketchip: re-add AXI4 interface 2016-11-22 17:27:58 -08:00
a140b07009 rocketchip: cut coreplex from rocketchip 2016-11-22 17:27:58 -08:00
3d644b943c coreplex: configString is a property of the RISCVPlatform 2016-11-21 21:13:26 -08:00
37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
10e459fedb rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem 2016-11-04 13:36:47 -07:00
aabd17d935 rocketchip: must create bundles within Module scope
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs

Solution: pass a bundle constructor to the cake base class

Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.

Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
2016-10-31 11:42:47 -07:00
ac886026e6 rocketchip: reduce number of type parameters 2016-10-31 11:42:47 -07:00
a73aa351ca rocketchip: fix all clock crossings 2016-10-31 11:42:13 -07:00
825c253a72 rocketchip: move TL2 and cake pattern into Coreplex 2016-10-31 11:42:13 -07:00
f8a0829134 rocketchip: remove clint; it moves into coreplex 2016-10-31 11:42:13 -07:00
3df797fcab rocketchip: replace TL1 MMIO with an example of TL2 MMIO 2016-10-31 11:41:18 -07:00
ec2d23b8b7 rocketchip: Bundle-slices need access to the outer LazyModule
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.

Now you can eat your cake too!
2016-10-31 11:41:18 -07:00
0ae45d0f24 rocketchip: bundle (=> B) need not be delayed; Module is constructed later 2016-10-31 11:41:18 -07:00
201e247f73 Factor coreplex IO connection into separate trait (#350)
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.

The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
2016-09-27 11:55:32 -07:00
d2df6397cd rename trc (tile reset clock) bundles to tcr (tile clock reset) 2016-09-21 18:29:28 -07:00
7afd630d3e add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
ed91e9a89b Merge remote-tracking branch 'origin' into testharness-refactor 2016-09-20 13:03:21 -07:00
7b8aa6c839 [rocketchip] split out Base and Example tops 2016-09-19 11:00:13 -07:00