53 lines
1.8 KiB
Scala
53 lines
1.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocketchip
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import Chisel._
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import config._
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import junctions._
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import rocketchip._
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/** Example Top with Periphery (w/o coreplex) */
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abstract class ExampleTop(implicit p: Parameters) extends BaseTop
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with PeripheryExtInterrupts
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with PeripheryMasterAXI4Mem
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with PeripheryMasterAXI4MMIO
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with PeripherySlaveAXI4 {
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override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
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}
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class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer)
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with PeripheryExtInterruptsBundle
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with PeripheryMasterAXI4MemBundle
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with PeripheryMasterAXI4MMIOBundle
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with PeripherySlaveAXI4Bundle
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class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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with PeripheryExtInterruptsModule
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with PeripheryMasterAXI4MemModule
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with PeripheryMasterAXI4MMIOModule
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with PeripherySlaveAXI4Module
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class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
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with PeripheryBootROM
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with PeripheryDTM
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with PeripheryCounter
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with HardwiredResetVector
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with RocketPlexMaster {
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override lazy val module = new ExampleRocketTopModule(this, () => new ExampleRocketTopBundle(this))
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}
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class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
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with PeripheryBootROMBundle
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with PeripheryDTMBundle
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with PeripheryCounterBundle
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with HardwiredResetVectorBundle
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with RocketPlexMasterBundle
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class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
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with PeripheryBootROMModule
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with PeripheryDTMModule
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with PeripheryCounterModule
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with HardwiredResetVectorModule
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with RocketPlexMasterModule
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