A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
* debug: Clean up Debug TransportModule synchronizer
With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.
I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
includes cases where they are used, but because they are not reset asynchronously,
a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
DTM and synchronizer is instantiated within Top, as it is a real piece of
hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.
To build Verilog which includes the JtagDTM within Top:
make CONFIG=WithJtagDTM_...
To test using gdb->OpenOCD->jtag_vpi->Verilog:
First, install openocd (included in this commit)
./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install
Then to run a simulation:
On a 32-bit core:
$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
--run ./simv-TestHarness-WithJtagDTM_... \
--cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
--freedom-e300-sim \
SimpleRegisterTest.test_s0
On a 64-bit core:
$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
--run ./simv-TestHarness-WithJtagDTM_... \
--cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
--freedom-u500-sim \
SimpleRegisterTest.test_s0
Initial cut
checkpoint which compiles and runs but there is some off-by-1 in the protocol
Debugging the clock crossing logic
checkpoint which works
Clean up the AsyncMailbox black box
