872 lines
29 KiB
Scala
872 lines
29 KiB
Scala
// See LICENSE for license details.
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package uncore.devices
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import Chisel._
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import junctions._
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import util._
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import regmapper._
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import uncore.tilelink2._
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import cde.{Parameters, Config, Field}
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// *****************************************
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// Constants which are interesting even
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// outside of this module
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// *****************************************
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object DbRegAddrs{
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def DMRAMBASE = UInt(0x0)
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def DMCONTROL = UInt(0x10)
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def DMINFO = UInt(0x11)
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def AUTHDATA0 = UInt(0x12)
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def AUTHDATA1 = UInt(0x13)
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def SERDATA = UInt(0x14)
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def SERSTATUS = UInt(0x15)
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def SBUSADDRESS0 = UInt(0x16)
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def SBUSADDRESS1 = UInt(0x17)
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def SBDATA0 = UInt(0x18)
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def SBDATA1 = UInt(0x19)
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//1a
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def HALTSUM = UInt(0x1B)
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//1c - 3b are the halt notification registers.
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def SBADDRESS2 = UInt(0x3d)
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// 3c
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def SBDATA2 = UInt(0x3e)
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def SBDATA3 = UInt(0x3f)
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}
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/** Constant values used by both Debug Bus Response & Request
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*/
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object DbBusConsts{
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def dbDataSize = 34
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def dbRamWordBits = 32
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def dbOpSize = 2
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def db_OP_NONE = UInt("b00")
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def db_OP_READ = UInt("b01")
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def db_OP_READ_WRITE = UInt("b10")
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def db_OP_READ_COND_WRITE = UInt("b11")
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def dbRespSize = 2
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def db_RESP_SUCCESS = UInt("b00")
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def db_RESP_FAILURE = UInt("b01")
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def db_RESP_HW_FAILURE = UInt("b10")
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// This is used outside this block
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// to indicate 'busy'.
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def db_RESP_RESERVED = UInt("b11")
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}
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object DsbBusConsts {
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def sbAddrWidth = 12
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def sbIdWidth = 10
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//These are the default ROM contents, which support RV32 and RV64.
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// See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
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// The code assumes 64 bytes of Debug RAM.
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def xlenAnyRomContents : Array[Byte] = Array(
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0x6f, 0x00, 0xc0, 0x04, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
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0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
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0xf3, 0x24, 0x00, 0xf1, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x24, 0xc0, 0x43,
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0x6f, 0x00, 0x80, 0x00, 0x83, 0x34, 0x80, 0x43, 0x23, 0x2e, 0x80, 0x42,
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0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b,
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0x13, 0x74, 0x84, 0x00, 0x63, 0x12, 0x04, 0x04, 0x73, 0x24, 0x20, 0x7b,
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0x73, 0x00, 0x20, 0x7b, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b,
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0x13, 0x74, 0x04, 0x1c, 0x13, 0x04, 0x04, 0xf4, 0x63, 0x1e, 0x04, 0x00,
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0x73, 0x24, 0x00, 0xf1, 0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0x42,
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0x67, 0x00, 0x00, 0x40, 0x23, 0x3c, 0x90, 0x42, 0x67, 0x00, 0x00, 0x40,
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0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10, 0x73, 0x60, 0x04, 0x7b,
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0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02, 0xe3, 0x0c, 0x04, 0xfe,
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0x6f, 0xf0, 0x1f, 0xfd).map(_.toByte)
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// These ROM contents support only RV32
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// See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
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// The code assumes only 28 bytes of Debug RAM.
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def xlen32OnlyRomContents : Array[Byte] = Array(
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0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
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0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
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0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
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0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
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0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
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0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
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0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x2c, 0x90, 0x40,
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0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
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0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
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0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
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// These ROM contents support only RV64
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// See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
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// The code assumes 64 bytes of Debug RAM.
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def xlen64OnlyRomContents : Array[Byte] = Array(
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0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
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0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
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0x83, 0x34, 0x80, 0x43, 0x23, 0x2e, 0x80, 0x42, 0x73, 0x24, 0x40, 0xf1,
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0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
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0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
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0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
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0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x3c, 0x90, 0x42,
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0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
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0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
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0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
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}
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object DsbRegAddrs{
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def CLEARDEBINT = 0x100
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def SETHALTNOT = 0x10C
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def SERINFO = 0x110
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def SERBASE = 0x114
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// For each serial, there are
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// 3 registers starting here:
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// SERSEND0
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// SERRECEIVE0
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// SERSTATUS0
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// ...
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// SERSTATUS7
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def SERTX_OFFSET = 0
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def SERRX_OFFSET = 4
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def SERSTAT_OFFSET = 8
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def RAMBASE = 0x400
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def ROMBASE = 0x800
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}
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// *****************************************
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// Configuration & Parameters for this Module
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//
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// *****************************************
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/** Enumerations used both in the hardware
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* and in the configuration specification.
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*/
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object DebugModuleAuthType extends scala.Enumeration {
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type DebugModuleAuthType = Value
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val None, Password, ChallengeResponse, Reserved = Value
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}
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import DebugModuleAuthType._
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object DebugModuleAccessType extends scala.Enumeration {
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type DebugModuleAccessType = Value
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val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value
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}
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import DebugModuleAccessType._
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/** Parameters exposed to the top-level design, set based on
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* external requirements, etc.
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*
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* This object checks that the parameters conform to the
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* full specification. The implementation which receives this
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* object can perform more checks on what that implementation
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* actually supports.
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* nComponents : The number of components to support debugging.
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* nDebugBusAddrSize : Size of the Debug Bus Address
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* nDebugRam Bytes: Size of the Debug RAM (depends on the XLEN of the machine).
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* debugRomContents: Optional Sequence of bytes which form the Debug ROM contents.
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* hasBusMaster: Whether or not a bus master should be included
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* The size of the accesses supported by the Bus Master.
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* nSerialPorts : Number of serial ports to instantiate
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* authType : The Authorization Type
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* Number of cycles to assert ndreset when pulsed.
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**/
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case class DebugModuleConfig (
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nComponents : Int,
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nDebugBusAddrSize : Int,
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nDebugRamBytes : Int,
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debugRomContents : Option[Seq[Byte]],
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hasBusMaster : Boolean,
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hasAccess128 : Boolean,
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hasAccess64 : Boolean,
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hasAccess32 : Boolean,
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hasAccess16 : Boolean,
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hasAccess8 : Boolean,
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nSerialPorts : Int,
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authType : DebugModuleAuthType,
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nNDResetCycles : Int
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) {
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if (hasBusMaster == false){
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require (hasAccess128 == false)
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require (hasAccess64 == false)
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require (hasAccess32 == false)
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require (hasAccess16 == false)
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require (hasAccess8 == false)
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}
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require (nSerialPorts <= 8)
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require ((nDebugBusAddrSize >= 5) && (nDebugBusAddrSize <= 7))
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private val maxComponents = nDebugBusAddrSize match {
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case 5 => (32*4)
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case 6 => (32*32)
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case 7 => (32*32)
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}
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require (nComponents > 0 && nComponents <= maxComponents)
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private val maxRam = nDebugBusAddrSize match {
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case 5 => (4 * 16)
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case 6 => (4 * 16)
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case 7 => (4 * 64)
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}
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require (nDebugRamBytes > 0 && nDebugRamBytes <= maxRam)
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val hasHaltSum = (nComponents > 64) || (nSerialPorts > 0)
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val hasDebugRom = debugRomContents.nonEmpty
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if (hasDebugRom) {
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require (debugRomContents.get.size > 0)
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require (debugRomContents.get.size <= 512)
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}
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require (nNDResetCycles > 0)
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}
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class DefaultDebugModuleConfig (val ncomponents : Int, val xlen:Int)
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extends DebugModuleConfig(
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nComponents = ncomponents,
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nDebugBusAddrSize = 5,
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// While smaller numbers are theoretically
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// possible as noted in the Spec,
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// the ROM image would need to be
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// adjusted accordingly.
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nDebugRamBytes = xlen match{
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case 32 => 28
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case 64 => 64
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case 128 => 64
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},
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debugRomContents = xlen match {
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case 32 => Some(DsbBusConsts.xlen32OnlyRomContents)
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case 64 => Some(DsbBusConsts.xlen64OnlyRomContents)
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},
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hasBusMaster = false,
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hasAccess128 = false,
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hasAccess64 = false,
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hasAccess32 = false,
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hasAccess16 = false,
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hasAccess8 = false,
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nSerialPorts = 0,
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authType = DebugModuleAuthType.None,
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nNDResetCycles = 1)
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case object DMKey extends Field[DebugModuleConfig]
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// *****************************************
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// Module Interfaces
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//
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// *****************************************
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/** Structure to define the contents of a Debug Bus Request
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*/
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class DebugBusReq(addrBits : Int) extends Bundle {
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val addr = UInt(width = addrBits)
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val data = UInt(width = DbBusConsts.dbDataSize)
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val op = UInt(width = DbBusConsts.dbOpSize)
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override def cloneType = new DebugBusReq(addrBits).asInstanceOf[this.type]
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}
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/** Structure to define the contents of a Debug Bus Response
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*/
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class DebugBusResp( ) extends Bundle {
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val data = UInt(width = DbBusConsts.dbDataSize)
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val resp = UInt(width = DbBusConsts.dbRespSize)
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}
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/** Structure to define the top-level DebugBus interface
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* of DebugModule.
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* DebugModule is the consumer of this interface.
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* Therefore it has the 'flipped' version of this.
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*/
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class DebugBusIO(implicit val p: cde.Parameters) extends ParameterizedBundle()(p) {
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val req = new DecoupledIO(new DebugBusReq(p(DMKey).nDebugBusAddrSize))
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val resp = new DecoupledIO(new DebugBusResp).flip()
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}
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trait HasDebugModuleParameters {
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val params : Parameters
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implicit val p = params
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val cfg = p(DMKey)
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}
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/** Debug Module I/O, with the exclusion of the RegisterRouter
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* Access interface.
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*/
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trait DebugModuleBundle extends Bundle with HasDebugModuleParameters {
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val db = new DebugBusIO()(p).flip()
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val debugInterrupts = Vec(cfg.nComponents, Bool()).asOutput
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val ndreset = Bool(OUTPUT)
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val fullreset = Bool(OUTPUT)
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}
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// *****************************************
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// The Module
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//
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// *****************************************
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/** Parameterized version of the Debug Module defined in the
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* RISC-V Debug Specification
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*
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* DebugModule is a slave to two masters:
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* The Debug Bus -- implemented as a generic Decoupled IO with request
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* and response channels
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* The System Bus -- implemented as generic RegisterRouter
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*
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* DebugModule is responsible for holding registers, RAM, and ROM
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* to support debug interactions, as well as driving interrupts
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* to a configurable number of components in the system.
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* It is also responsible for some reset lines.
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*/
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trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
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val io: DebugModuleBundle
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//--------------------------------------------------------------
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// Import constants for shorter variable names
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//--------------------------------------------------------------
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import DbRegAddrs._
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import DsbRegAddrs._
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import DsbBusConsts._
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import DbBusConsts._
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//--------------------------------------------------------------
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// Sanity Check Configuration For this implementation.
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//--------------------------------------------------------------
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require (cfg.nComponents <= 128)
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require (cfg.nSerialPorts == 0)
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require (cfg.hasBusMaster == false)
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require (cfg.nDebugRamBytes <= 64)
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require (cfg.authType == DebugModuleAuthType.None)
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require((DbBusConsts.dbRamWordBits % 8) == 0)
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//--------------------------------------------------------------
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// Private Classes (Register Fields)
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//--------------------------------------------------------------
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class RAMFields() extends Bundle {
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val interrupt = Bool()
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val haltnot = Bool()
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val data = Bits(width = 32)
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override def cloneType = new RAMFields().asInstanceOf[this.type]
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}
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class CONTROLFields() extends Bundle {
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val interrupt = Bool()
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val haltnot = Bool()
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val reserved0 = Bits(width = 31-22 + 1)
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val buserror = Bits(width = 3)
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val serial = Bits(width = 3)
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val autoincrement = Bool()
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val access = UInt(width = 3)
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val hartid = Bits(width = 10)
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val ndreset = Bool()
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val fullreset = Bool()
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override def cloneType = new CONTROLFields().asInstanceOf[this.type]
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}
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class DMINFOFields() extends Bundle {
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val reserved0 = Bits(width = 2)
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val abussize = UInt(width = 7)
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val serialcount = UInt(width = 4)
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val access128 = Bool()
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val access64 = Bool()
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val access32 = Bool()
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val access16 = Bool()
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val accesss8 = Bool()
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val dramsize = UInt(width = 6)
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val haltsum = Bool()
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val reserved1 = Bits(width = 3)
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val authenticated = Bool()
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val authbusy = Bool()
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val authtype = UInt(width = 2)
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val version = UInt(width = 2)
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override def cloneType = new DMINFOFields().asInstanceOf[this.type]
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}
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class HALTSUMFields() extends Bundle {
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val serialfull = Bool()
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val serialvalid = Bool()
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val acks = Bits(width = 32)
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override def cloneType = new HALTSUMFields().asInstanceOf[this.type]
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}
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//--------------------------------------------------------------
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// Register & Wire Declarations
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//--------------------------------------------------------------
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// --- Debug Bus Registers
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val CONTROLReset = Wire(new CONTROLFields())
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val CONTROLWrEn = Wire(Bool())
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val CONTROLReg = Reg(new CONTROLFields())
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val CONTROLWrData = Wire (new CONTROLFields())
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val CONTROLRdData = Wire (new CONTROLFields())
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val ndresetCtrReg = Reg(UInt(cfg.nNDResetCycles))
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val DMINFORdData = Wire (new DMINFOFields())
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val HALTSUMRdData = Wire (new HALTSUMFields())
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val RAMWrData = Wire (new RAMFields())
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val RAMRdData = Wire (new RAMFields())
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// --- System Bus Registers
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val SETHALTNOTWrEn = Wire(Bool())
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val SETHALTNOTWrData = Wire(UInt(width = sbIdWidth))
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val CLEARDEBINTWrEn = Wire(Bool())
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val CLEARDEBINTWrData = Wire(UInt(width = sbIdWidth))
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// --- Interrupt & Halt Notification Registers
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val interruptRegs = Reg(init=Vec.fill(cfg.nComponents){Bool(false)})
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val haltnotRegs = Reg(init=Vec.fill(cfg.nComponents){Bool(false)})
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val numHaltnotStatus = ((cfg.nComponents - 1) / 32) + 1
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val haltnotStatus = Wire(Vec(numHaltnotStatus, Bits(width = 32)))
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val rdHaltnotStatus = Wire(Bits(width = 32))
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val haltnotSummary = Cat(haltnotStatus.map(_.orR).reverse)
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|
// --- Debug RAM
|
|
|
|
val ramDataWidth = DbBusConsts.dbRamWordBits
|
|
val ramDataBytes = ramDataWidth / 8;
|
|
val ramAddrWidth = log2Up(cfg.nDebugRamBytes / ramDataBytes)
|
|
|
|
val ramMem = Reg(init = Vec.fill(cfg.nDebugRamBytes){UInt(0, width = 8)})
|
|
|
|
val dbRamAddr = Wire(UInt(width=ramAddrWidth))
|
|
val dbRamAddrValid = Wire(Bool())
|
|
val dbRamRdData = Wire (UInt(width=ramDataWidth))
|
|
val dbRamWrData = Wire(UInt(width=ramDataWidth))
|
|
val dbRamWrEn = Wire(Bool())
|
|
val dbRamRdEn = Wire(Bool())
|
|
val dbRamWrEnFinal = Wire(Bool())
|
|
val dbRamRdEnFinal = Wire(Bool())
|
|
|
|
// --- Debug Bus Accesses
|
|
|
|
val dbRdEn = Wire(Bool())
|
|
val dbWrEn = Wire(Bool())
|
|
val dbRdData = Wire(UInt(width = DbBusConsts.dbDataSize))
|
|
|
|
val s_DB_READY :: s_DB_RESP :: Nil = Enum(Bits(), 2)
|
|
val dbStateReg = Reg(init = s_DB_READY)
|
|
|
|
val dbResult = Wire(io.db.resp.bits)
|
|
|
|
val dbReq = Wire(io.db.req.bits)
|
|
val dbRespReg = Reg(io.db.resp.bits)
|
|
|
|
val rdCondWrFailure = Wire(Bool())
|
|
val dbWrNeeded = Wire(Bool())
|
|
|
|
//--------------------------------------------------------------
|
|
// Interrupt Registers
|
|
//--------------------------------------------------------------
|
|
|
|
for (component <- 0 until cfg.nComponents) {
|
|
io.debugInterrupts(component) := interruptRegs(component)
|
|
}
|
|
|
|
// Interrupt Registers are written by write to CONTROL or debugRAM addresses
|
|
// for Debug Bus, and cleared by writes to CLEARDEBINT by System Bus.
|
|
// It is "unspecified" what should happen if both
|
|
// SET and CLEAR happen at the same time. In this
|
|
// implementation, the SET wins.
|
|
|
|
for (component <- 0 until cfg.nComponents) {
|
|
when (CONTROLWrEn) {
|
|
when (CONTROLWrData.hartid === UInt(component)) {
|
|
interruptRegs(component) := interruptRegs(component) | CONTROLWrData.interrupt
|
|
}
|
|
}.elsewhen (dbRamWrEn) {
|
|
when (CONTROLReg.hartid === UInt(component)){
|
|
interruptRegs(component) := interruptRegs(component) | RAMWrData.interrupt
|
|
}
|
|
}.elsewhen (CLEARDEBINTWrEn){
|
|
when (CLEARDEBINTWrData === UInt(component, width = sbIdWidth)) {
|
|
interruptRegs(component) := Bool(false)
|
|
}
|
|
}
|
|
}
|
|
|
|
//--------------------------------------------------------------
|
|
// Halt Notification Registers
|
|
//--------------------------------------------------------------
|
|
|
|
// Halt Notifications Registers are cleared by zero write to CONTROL or debugRAM addresses
|
|
// for Debug Bus, and set by write to SETHALTNOT by System Bus.
|
|
// It is "unspecified" what should happen if both
|
|
// SET and CLEAR happen at the same time. In this
|
|
// implementation, the SET wins.
|
|
|
|
for (component <- 0 until cfg.nComponents) {
|
|
when (SETHALTNOTWrEn){
|
|
when (SETHALTNOTWrData === UInt(component, width = sbIdWidth)) {
|
|
haltnotRegs(component) := Bool(true)
|
|
}
|
|
} .elsewhen (CONTROLWrEn) {
|
|
when (CONTROLWrData.hartid === UInt(component)) {
|
|
haltnotRegs(component) := haltnotRegs(component) & CONTROLWrData.haltnot
|
|
}
|
|
}.elsewhen (dbRamWrEn) {
|
|
when (CONTROLReg.hartid === UInt(component)){
|
|
haltnotRegs(component) := haltnotRegs(component) & RAMWrData.haltnot
|
|
}
|
|
}
|
|
}
|
|
|
|
for (ii <- 0 until numHaltnotStatus) {
|
|
haltnotStatus(ii) := Cat(haltnotRegs.slice(ii * 32, (ii + 1) * 32).reverse)
|
|
}
|
|
|
|
//--------------------------------------------------------------
|
|
// Other Registers
|
|
//--------------------------------------------------------------
|
|
|
|
CONTROLReset.interrupt := Bool(false)
|
|
CONTROLReset.haltnot := Bool(false)
|
|
CONTROLReset.reserved0 := Bits(0)
|
|
CONTROLReset.buserror := Bits(0)
|
|
CONTROLReset.serial := Bits(0)
|
|
CONTROLReset.autoincrement := Bool(false)
|
|
CONTROLReset.access := UInt(DebugModuleAccessType.Access32Bit.id)
|
|
CONTROLReset.hartid := Bits(0)
|
|
CONTROLReset.ndreset := Bool(false)
|
|
CONTROLReset.fullreset := Bool(false)
|
|
|
|
// Because this version of DebugModule doesn't
|
|
// support authentication, this entire register is
|
|
// Read-Only constant wires.
|
|
DMINFORdData.reserved0 := Bits(0)
|
|
DMINFORdData.abussize := UInt(0) // Not Implemented.
|
|
DMINFORdData.serialcount := UInt(cfg.nSerialPorts)
|
|
DMINFORdData.access128 := Bool(cfg.hasAccess128)
|
|
DMINFORdData.access64 := Bool(cfg.hasAccess64)
|
|
DMINFORdData.access32 := Bool(cfg.hasAccess32)
|
|
DMINFORdData.access16 := Bool(cfg.hasAccess16)
|
|
DMINFORdData.accesss8 := Bool(cfg.hasAccess8)
|
|
DMINFORdData.dramsize := Bits((cfg.nDebugRamBytes >> 2) - 1) // Size in 32-bit words minus 1.
|
|
DMINFORdData.haltsum := Bool(cfg.hasHaltSum)
|
|
DMINFORdData.reserved1 := Bits(0)
|
|
DMINFORdData.authenticated := Bool(true) // Not Implemented.
|
|
DMINFORdData.authbusy := Bool(false) // Not Implemented.
|
|
DMINFORdData.authtype := UInt(cfg.authType.id)
|
|
DMINFORdData.version := UInt(1) // Conforms to RISC-V Debug Spec
|
|
|
|
HALTSUMRdData.serialfull := Bool(false) // Not Implemented
|
|
HALTSUMRdData.serialvalid := Bool(false) // Not Implemented
|
|
HALTSUMRdData.acks := haltnotSummary
|
|
|
|
//--------------------------------------------------------------
|
|
// Debug RAM Access (Debug Bus ... System Bus can override)
|
|
//--------------------------------------------------------------
|
|
|
|
dbReq := io.db.req.bits
|
|
// Debug Bus RAM Access
|
|
// From Specification: Debug RAM is 0x00 - 0x0F
|
|
// 0x40 - 0x6F Not Implemented
|
|
dbRamAddr := dbReq.addr( ramAddrWidth-1 , 0)
|
|
dbRamWrData := dbReq.data
|
|
dbRamAddrValid := Bool(true)
|
|
if (ramAddrWidth < 4){
|
|
dbRamAddrValid := (dbReq.addr(3, ramAddrWidth) === UInt(0))
|
|
}
|
|
|
|
val dbRamRdDataFields = List.tabulate(cfg.nDebugRamBytes / ramDataBytes) { ii =>
|
|
val slice = ramMem.slice(ii * ramDataBytes, (ii+1)*ramDataBytes)
|
|
slice.reduce[UInt]{ case (x: UInt, y: UInt) => Cat(y, x)}
|
|
}
|
|
|
|
dbRamRdData := dbRamRdDataFields(dbRamAddr)
|
|
|
|
when (dbRamWrEnFinal) {
|
|
for (ii <- 0 until ramDataBytes) {
|
|
ramMem(dbRamAddr * UInt(ramDataBytes) + UInt(ii)) := dbRamWrData((8*(ii+1)-1), (8*ii))
|
|
}
|
|
}
|
|
|
|
//--------------------------------------------------------------
|
|
// Debug Bus Access
|
|
//--------------------------------------------------------------
|
|
|
|
// 0x00 - 0x0F Debug RAM
|
|
// 0x10 - 0x1B Registers
|
|
// 0x1C - 0x3B Halt Notification Registers
|
|
// 0x3C - 0x3F Registers
|
|
// 0x40 - 0x6F Debug RAM
|
|
|
|
|
|
// -----------------------------------------
|
|
// DB Access Write Decoder
|
|
|
|
CONTROLWrData := new CONTROLFields().fromBits(dbReq.data)
|
|
RAMWrData := new RAMFields().fromBits(dbReq.data)
|
|
|
|
dbRamWrEn := Bool(false)
|
|
dbRamWrEnFinal := Bool(false)
|
|
CONTROLWrEn := Bool(false)
|
|
when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
|
|
dbRamWrEn := dbWrEn
|
|
when (dbRamAddrValid) {
|
|
dbRamWrEnFinal := dbWrEn
|
|
}
|
|
}.elsewhen (dbReq.addr === DMCONTROL) {
|
|
CONTROLWrEn := dbWrEn
|
|
}.otherwise {
|
|
//Other registers/RAM are Not Implemented.
|
|
}
|
|
|
|
when (reset) {
|
|
CONTROLReg := CONTROLReset
|
|
ndresetCtrReg := UInt(0)
|
|
}.elsewhen (CONTROLWrEn) {
|
|
// interrupt handled in other logic
|
|
// haltnot handled in other logic
|
|
if (cfg.hasBusMaster){
|
|
// buserror is set 'until 0 is written to any bit in this field'.
|
|
CONTROLReg.buserror := Mux(CONTROLWrData.buserror.andR, CONTROLReg.buserror, UInt(0))
|
|
CONTROLReg.autoincrement := CONTROLWrData.autoincrement
|
|
CONTROLReg.access := CONTROLWrData.access
|
|
}
|
|
if (cfg.nSerialPorts > 0){
|
|
CONTROLReg.serial := CONTROLWrData.serial
|
|
}
|
|
CONTROLReg.hartid := CONTROLWrData.hartid
|
|
CONTROLReg.fullreset := CONTROLReg.fullreset | CONTROLWrData.fullreset
|
|
when (CONTROLWrData.ndreset){
|
|
ndresetCtrReg := UInt(cfg.nNDResetCycles)
|
|
}.otherwise {
|
|
ndresetCtrReg := Mux(ndresetCtrReg === UInt(0) , UInt(0), ndresetCtrReg - UInt(1))
|
|
}
|
|
}.otherwise {
|
|
ndresetCtrReg := Mux(ndresetCtrReg === UInt(0) , UInt(0), ndresetCtrReg - UInt(1))
|
|
}
|
|
|
|
// -----------------------------------------
|
|
// DB Access Read Mux
|
|
|
|
CONTROLRdData := CONTROLReg;
|
|
CONTROLRdData.interrupt := interruptRegs(CONTROLReg.hartid)
|
|
CONTROLRdData.haltnot := haltnotRegs(CONTROLReg.hartid)
|
|
CONTROLRdData.ndreset := ndresetCtrReg.orR
|
|
|
|
RAMRdData.interrupt := interruptRegs(CONTROLReg.hartid)
|
|
RAMRdData.haltnot := haltnotRegs(CONTROLReg.hartid)
|
|
RAMRdData.data := dbRamRdData
|
|
|
|
dbRdData := UInt(0)
|
|
|
|
// Higher numbers of numHaltnotStatus Not Implemented.
|
|
// This logic assumes only up to 128 components.
|
|
rdHaltnotStatus := Bits(0)
|
|
for (ii <- 0 until numHaltnotStatus) {
|
|
when (dbReq.addr === UInt(ii)) {
|
|
rdHaltnotStatus := haltnotStatus(ii)
|
|
}
|
|
}
|
|
|
|
dbRamRdEn := Bool(false)
|
|
dbRamRdEnFinal := Bool(false)
|
|
when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
|
|
dbRamRdEn := dbRdEn
|
|
when (dbRamAddrValid) {
|
|
dbRdData := RAMRdData.asUInt
|
|
dbRamRdEnFinal := dbRdEn
|
|
}
|
|
}.elsewhen (dbReq.addr === DMCONTROL) {
|
|
dbRdData := CONTROLRdData.asUInt
|
|
}.elsewhen (dbReq.addr === DMINFO) {
|
|
dbRdData := DMINFORdData.asUInt
|
|
}.elsewhen (dbReq.addr === HALTSUM) {
|
|
if (cfg.hasHaltSum){
|
|
dbRdData := HALTSUMRdData.asUInt
|
|
} else {
|
|
dbRdData := UInt(0)
|
|
}
|
|
}.elsewhen ((dbReq.addr >> 2) === UInt(7)) { // 0x1C - 0x1F Haltnot
|
|
dbRdData := rdHaltnotStatus
|
|
} .otherwise {
|
|
//These Registers are not implemented in this version of DebugModule:
|
|
// AUTHDATA0
|
|
// AUTHDATA1
|
|
// SERDATA
|
|
// SERSTATUS
|
|
// SBUSADDRESS0
|
|
// SBUSADDRESS1
|
|
// SBDATA0
|
|
// SBDATA1
|
|
// SBADDRESS2
|
|
// SBDATA2
|
|
// SBDATA3
|
|
// 0x20 - 0x3B haltnot
|
|
// Upper bytes of Debug RAM.
|
|
dbRdData := UInt(0)
|
|
}
|
|
|
|
// Conditional write fails if MSB is set of the read data.
|
|
rdCondWrFailure := dbRdData(dbDataSize - 1 ) &&
|
|
(dbReq.op === db_OP_READ_COND_WRITE)
|
|
|
|
dbWrNeeded := (dbReq.op === db_OP_READ_WRITE) ||
|
|
((dbReq.op === db_OP_READ_COND_WRITE) && ~rdCondWrFailure)
|
|
|
|
// This is only relevant at end of s_DB_READ.
|
|
dbResult.resp := Mux(rdCondWrFailure,
|
|
db_RESP_FAILURE,
|
|
db_RESP_SUCCESS)
|
|
dbResult.data := dbRdData
|
|
|
|
// -----------------------------------------
|
|
// DB Access State Machine Decode (Combo)
|
|
io.db.req.ready := (dbStateReg === s_DB_READY) ||
|
|
(dbStateReg === s_DB_RESP && io.db.resp.fire())
|
|
|
|
io.db.resp.valid := (dbStateReg === s_DB_RESP)
|
|
io.db.resp.bits := dbRespReg
|
|
|
|
dbRdEn := io.db.req.fire()
|
|
dbWrEn := dbWrNeeded && io.db.req.fire()
|
|
|
|
// -----------------------------------------
|
|
// DB Access State Machine Update (Seq)
|
|
|
|
when (dbStateReg === s_DB_READY){
|
|
when (io.db.req.fire()){
|
|
dbStateReg := s_DB_RESP
|
|
dbRespReg := dbResult
|
|
}
|
|
} .elsewhen (dbStateReg === s_DB_RESP){
|
|
when (io.db.req.fire()){
|
|
dbStateReg := s_DB_RESP
|
|
dbRespReg := dbResult
|
|
}.elsewhen (io.db.resp.fire()){
|
|
dbStateReg := s_DB_READY
|
|
}
|
|
}
|
|
|
|
|
|
//--------------------------------------------------------------
|
|
// Debug ROM
|
|
//--------------------------------------------------------------
|
|
|
|
val romRegFields = if (cfg.hasDebugRom) {
|
|
// Inspired by ROMSlave
|
|
val romContents = cfg.debugRomContents.get
|
|
val romByteWidth = ramDataWidth / 8
|
|
val romRows = (romContents.size + romByteWidth - 1)/romByteWidth
|
|
List.tabulate(romRows) { ii => {
|
|
val slice = romContents.slice(ii*romByteWidth, (ii+1)*romByteWidth)
|
|
val line = UInt(slice.foldRight(BigInt(0)) { case (x,y) => ((y << 8) + (x.toInt & 0xFF))}, width = romByteWidth*8)
|
|
RegField.r(ramDataWidth, line)
|
|
}
|
|
}
|
|
} else {
|
|
Seq(RegField(ramDataWidth))
|
|
}
|
|
|
|
//--------------------------------------------------------------
|
|
// System Bus Access
|
|
//--------------------------------------------------------------
|
|
|
|
// Local reg mapper function : Notify when written, but give the value.
|
|
def wValue (n: Int, value: UInt, set: Bool) : RegField = {
|
|
RegField(n, value, RegWriteFn((valid, data) => {set := valid ; value := data; Bool(true)}))
|
|
}
|
|
|
|
regmap(
|
|
CLEARDEBINT -> Seq(wValue(sbIdWidth, CLEARDEBINTWrData, CLEARDEBINTWrEn)),
|
|
SETHALTNOT -> Seq(wValue(sbIdWidth, SETHALTNOTWrData, SETHALTNOTWrEn)),
|
|
RAMBASE -> ramMem.map(x => RegField(8, x)),
|
|
ROMBASE -> romRegFields
|
|
)
|
|
|
|
//--------------------------------------------------------------
|
|
// Misc. Outputs
|
|
//--------------------------------------------------------------
|
|
|
|
io.ndreset := ndresetCtrReg.orR
|
|
io.fullreset := CONTROLReg.fullreset
|
|
|
|
}
|
|
|
|
/** Create a concrete TL2 Slave for the DebugModule RegMapper interface.
|
|
*
|
|
*/
|
|
|
|
class TLDebugModule(beatBytes: Int) (implicit p: Parameters)
|
|
extends TLRegisterRouter(0x0, beatBytes=beatBytes)(
|
|
new TLRegBundle(p, _ ) with DebugModuleBundle)(
|
|
new TLRegModule(p, _, _) with DebugModule)
|
|
|
|
|
|
/** Synchronizers for DebugBus
|
|
*
|
|
*/
|
|
|
|
|
|
object AsyncDebugBusCrossing {
|
|
// takes from_source from the 'from' clock domain to the 'to' clock domain
|
|
def apply(from_clock: Clock, from_reset: Bool, from_source: DebugBusIO, to_clock: Clock, to_reset: Bool, depth: Int = 1, sync: Int = 3) = {
|
|
val to_sink = Wire(new DebugBusIO()(from_source.p))
|
|
to_sink.req <> AsyncDecoupledCrossing(from_clock, from_reset, from_source.req, to_clock, to_reset, depth, sync)
|
|
from_source.resp <> AsyncDecoupledCrossing(to_clock, to_reset, to_sink.resp, from_clock, from_reset, depth, sync)
|
|
to_sink // is now to_source
|
|
}
|
|
}
|
|
|
|
|
|
object AsyncDebugBusFrom { // OutsideClockDomain
|
|
// takes from_source from the 'from' clock domain and puts it into your clock domain
|
|
def apply(from_clock: Clock, from_reset: Bool, from_source: DebugBusIO, depth: Int = 1, sync: Int = 3): DebugBusIO = {
|
|
val scope = AsyncScope()
|
|
AsyncDebugBusCrossing(from_clock, from_reset, from_source, scope.clock, scope.reset, depth, sync)
|
|
}
|
|
}
|
|
|
|
object AsyncDebugBusTo { // OutsideClockDomain
|
|
// takes source from your clock domain and puts it into the 'to' clock domain
|
|
def apply(to_clock: Clock, to_reset: Bool, source: DebugBusIO, depth: Int = 1, sync: Int = 3): DebugBusIO = {
|
|
val scope = AsyncScope()
|
|
AsyncDebugBusCrossing(scope.clock, scope.reset, source, to_clock, to_reset, depth, sync)
|
|
}
|
|
}
|