Megan Wachs
e9e05b5f3b
Add a check that MaxHartIdBits is enough for all hartids ( #1054 )
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* Add a check that MaxHartIdBits is enough for all hartids
* Correct off-by-one error in hartid check
2017-10-13 15:20:35 -07:00
Henry Cook
1852ccd8f3
Merge pull request #1053 from freechipsproject/resource-cacheable
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tilelink: cacheable resource permission
2017-10-12 17:49:49 -07:00
Wesley W. Terpstra
8b58327fa4
axi4: conversion from TL does not need beatBytes ( #1051 )
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We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
2017-10-12 16:41:54 -07:00
Andrew Waterman
21b5367259
Expand C.UNIMP correctly ( #1052 )
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It was expanding to AMOADD.W, which is clearly not an illegal instruction.
2017-10-12 14:00:14 -07:00
Henry Cook
ad243ef9f5
tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so
2017-10-12 13:49:40 -07:00
Henry Cook
ad543e5bb6
Merge pull request #1050 from freechipsproject/uncacheable-tims
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rocket: TIMs should never be cached
2017-10-12 13:04:00 -07:00
Wesley W. Terpstra
f82e441426
axi4: implement a diplomatic AXI4 clock crossing ( #1049 )
2017-10-12 00:05:45 -07:00
Henry Cook
66e4bfc2d9
rocket: TIMs should never be cached
2017-10-11 18:22:52 -07:00
Henry Cook
b64609bfe8
Merge pull request #1039 from freechipsproject/tile-crossing-params
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Improvements wrt connecting RocketTiles to SystemBus
2017-10-11 17:12:03 -07:00
Henry Cook
024ccd8ac2
Merge pull request #1048 from freechipsproject/local_int_hookup
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Correctly hook up the Local Interrupts into the Coreplex.
2017-10-11 17:08:24 -07:00
Megan Wachs
7b4c48d005
Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars
2017-10-11 15:10:50 -07:00
Henry Cook
60934ac622
coreplex: TilePortParams use BasicBusBlockers
2017-10-11 13:36:46 -07:00
Henry Cook
2dbe882e58
tilelink: add BasicBusBlocker device
2017-10-11 13:36:42 -07:00
Henry Cook
9f8e3d8879
tilelink: BusBypass can be sent to DeadlockDevice
2017-10-11 12:45:36 -07:00
Henry Cook
ec056535dc
tilelink: add DeadlockDevice
2017-10-11 12:44:23 -07:00
Wesley W. Terpstra
b566ffedea
system: fix DefaultFPGAConfig ( #1047 )
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It was missing cores. Fixes #736 .
2017-10-11 10:48:41 -07:00
Wesley W. Terpstra
8e1a002c4e
Merge pull request #1033 from freechipsproject/dont-touch
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Use chisel3.experimental.dontTouch (take 2)
2017-10-11 00:59:37 -07:00
Henry Cook
329a5c35d4
tilelink: unsafe cache cork discards outer d.sink
2017-10-11 00:30:51 -07:00
Henry Cook
1240cb275c
coreplex: TilePortParams formatting
2017-10-11 00:29:11 -07:00
Wesley W. Terpstra
6f3a4cd733
build: pass annotations to firrtl
2017-10-10 23:42:55 -07:00
Wesley W. Terpstra
5d62c321f4
generator: create annotation file
2017-10-10 23:23:06 -07:00
Henry Cook
75345b6048
rocket: don't remove ports on top module
2017-10-10 21:28:59 -07:00
Wesley W. Terpstra
5ff4c1674a
Merge pull request #1044 from freechipsproject/nicer-clint
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clint: use RegField.toBytes to save some work
2017-10-10 20:33:00 -07:00
Wesley W. Terpstra
b3bdf5eca6
RegField: default argument for .bytes
2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
e094b94ce5
clint: use RegField.toBytes to save some work
2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
10472b4296
diplomacy: auto connect bundles in a stable order ( #1045 )
2017-10-10 19:41:46 -07:00
Henry Cook
1867a5b226
rocket: only cache when AcquireT is possible
2017-10-10 18:06:58 -07:00
Andrew Waterman
b2bc46471b
Conditionalize some covers that are sometimes impossible ( #1043 )
2017-10-10 17:14:33 -07:00
Richard Xia
ef28ce8d2f
Merge pull request #1042 from freechipsproject/bump-riscv-tools
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Bump riscv-tools.
2017-10-10 16:31:38 -07:00
Henry Cook
37406706b4
coreplex: move CacheCork in front of SBus
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Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
2017-10-10 16:24:32 -07:00
Henry Cook
8f5f80f958
coreplex: TileSlavePortParams inject adapters into PBus
2017-10-10 15:25:08 -07:00
Henry Cook
660355004e
coreplex: TileMasterPortParams inject adapters into SBus
2017-10-10 15:02:50 -07:00
Richard Xia
167aa7b793
Bump riscv-tools.
2017-10-10 14:14:10 -07:00
Andrew Waterman
50429daef4
Merge pull request #1036 from freechipsproject/l1-cover
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Add some covers for L1 memory system
2017-10-10 12:28:48 -07:00
Henry Cook
9026646459
coreplex: first cut at using RocketCrossingParams
2017-10-10 12:02:04 -07:00
Wesley W. Terpstra
d6766a8c68
RocketTile: make sure 'hartid' is available for traits ( #1037 )
2017-10-09 21:03:18 -07:00
Andrew Waterman
a9686ab883
Merge pull request #1035 from freechipsproject/big-paddr
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Fix paddrBits < xLen && paddrBits == vaddrBits case
2017-10-09 20:59:21 -07:00
Andrew Waterman
1474ab438d
Remove extraneous signal
2017-10-09 18:33:50 -07:00
Andrew Waterman
f3825270c1
Add some covers for L1 memory system
2017-10-09 18:33:36 -07:00
Andrew Waterman
2c4009a138
Fix paddrBits < xLen && paddrBits == vaddrBits case
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Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
2017-10-09 16:48:04 -07:00
Megan Wachs
0e6aa7ae9d
Merge pull request #1024 from freechipsproject/jtag_coverage
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Add Coverage points for JTAG TAP
2017-10-09 12:29:18 -07:00
Andrew Waterman
d78ad857ee
Merge pull request #1034 from freechipsproject/base-tile
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Generalize Tile/Coreplex hierarchy
2017-10-09 11:42:20 -07:00
Megan Wachs
0916cf1bdd
JTAG Coverage: Correct jtag_reset case
2017-10-09 09:54:15 -07:00
Megan Wachs
9efe1c448e
Merge remote-tracking branch 'origin/master' into HEAD
2017-10-09 09:48:38 -07:00
Andrew Waterman
986cbfb6b1
For Rockets without VM, widen vaddrBits to paddrBits
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This supports addressing a >39-bit physical address space.
2017-10-08 01:21:47 -07:00
Andrew Waterman
a0e5a20b60
Don't route branch comparison result through ALU output mux
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This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
2017-10-07 17:36:24 -07:00
Andrew Waterman
36c39d01e4
Factor out most of HasRocketTiles into HasTiles
2017-10-07 17:36:24 -07:00
Andrew Waterman
70a4127cb8
Factor out some of HaveRocketTiles into HaveTiles
2017-10-07 17:36:24 -07:00
Andrew Waterman
34e96c03b1
Move HCF to BaseTile
2017-10-07 17:36:24 -07:00
Andrew Waterman
71205b70cc
Make RocketTileWrapper a BaseTile
2017-10-07 17:36:24 -07:00