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25 Commits

Author SHA1 Message Date
Wesley W. Terpstra 66f64a9759 tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) 
idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
 2017-06-26 17:54:17 -07:00
Wesley W. Terpstra 8ca6c10994 tilelink2: ToAXI4 can strip off low source ID bits 
Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.

This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
 2017-06-23 17:22:45 -07:00
Wesley W. Terpstra 87a5665e43 axi4: only block writes if SAME master has outstanding reads (#782) 
* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
 2017-06-05 16:54:00 -07:00
Wesley W. Terpstra d25ad10592 diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Wesley W. Terpstra 9317a00896 tilelink2: ToAXI4, sort and print AXI IDs used 2017-06-02 14:27:37 -07:00
Wesley W. Terpstra 4847c32599 tilelink: ToAXI4 - must interlock till last beat 
AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
 2017-05-08 00:17:06 -07:00
Wesley W. Terpstra 58a4529cc5 axi4: the last missing piece for safe FIFO ordering 2017-05-01 22:53:41 -07:00
Wesley W. Terpstra d27e1928dd axi4: make maxFlight a per-master parameter 2017-05-01 22:53:40 -07:00
Wesley W. Terpstra 9f08c484bd tilelink2: ToAXI4 provide FIFO order semantics 2017-05-01 22:53:40 -07:00
Jacob Chang 1c6dde8c15 Make parameters for TLToAHB and TLToAXI4 accessable (#581) 2017-03-10 22:26:38 -08:00
Wesley W. Terpstra cfd367248f rocketchip: add blind ports to DTS 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 972953868c uncore: switch to new diplomacy Node API 
Most adapters should work on multiple ports.
This patch changes them all.
 2017-01-29 15:54:45 -08:00
Wesley W. Terpstra 6ff35a387a tilelink2: disable A=>D bypass in ToAXI4 whenever possible 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra 64e1de751d axi4: add a minLatency parameter 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Wesley W. Terpstra 020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Wesley W. Terpstra b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Henry Cook c0efd247b0 [tl2] expand firstlast api and L1WB bugfix 2016-11-14 12:12:31 -08:00
Wesley W. Terpstra d067e87a7d tilelink2 Parameters: sinkId is per port, not per manager 2016-11-03 14:37:17 -07:00
Wesley W. Terpstra 4d50733548 tilelink2 ToAXI4: use helper method for a_last (#418) 2016-10-25 10:16:42 -07:00
Wesley W. Terpstra 0aebf9e341 tilelink2 ToAXI4: no arbitration path register needed 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra a423f97844 axi4: parameterized AXI master constraint for aligned access 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra 673cf1fdb5 tilelink2 ToAXI4: must create irrevocable D for now 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra 8e92ac32b7 tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra adf5f1807b tilelink2: ToAXI4 bridge added 2016-10-10 11:21:50 -07:00