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Commit Graph

67 Commits

Author SHA1 Message Date
593839e0d5 Debug: add Debug regression to Travis regressions. 2018-01-05 16:10:00 -08:00
4449dd0baa Debug regressions: Add necessary config scripts 2018-01-05 16:03:59 -08:00
e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
d5a135914b Revert "Disable AMBAUnitTestConfig, as it is blocking unrelated PRs"
This reverts commit 39b7e930ca.

Now that the RAMModel can properly tolerate overlapping responses
in the face of source reuse, we can re-enable the regression test.
2017-08-07 16:04:02 -07:00
39b7e930ca Disable AMBAUnitTestConfig, as it is blocking unrelated PRs 2017-08-05 16:14:02 -07:00
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
2017-07-07 10:48:16 -07:00
304e82486f Debug: Update makefile now that OpenOCD is part of riscv-tools 2017-05-18 18:46:46 -07:00
4acc302158 unittest: disable XBar test from regression (covered by other tests) 2017-05-17 14:02:59 -07:00
23706113c2 Bump riscv-tools, to get some -mcmodel=medany fixes (#739) 2017-05-11 21:04:32 -07:00
9a6e7afc93 debug: bump OpenOCD to latest version of newprogram (with Examined RISC-V core message) 2017-04-17 10:28:33 -07:00
c5cb8b714f debug: Bump version and location of OpenOCD to pick up fix for off-by-1 in hartsel 2017-04-17 10:28:33 -07:00
c5b0b6fb85 debug: bump openOCD version to pick up read_mem fix. Use MemTest64 instead because it's more likely to fail than SimpleS0Test 2017-04-05 15:14:32 -07:00
d2c1bdc2ce Debug Controls (#639)
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
2017-04-03 13:31:35 -07:00
861651587b debug: Update Makefile to use new OpenOCD and allow for easier debugging. (#619) 2017-03-27 15:52:04 -07:00
d4272db067 travis: only run 4 jobs at once (#593)
We can only run 4 at a time; 5 causes the test time to double.
In the past we had a 50minute build deadline, but that's fixed.
2017-03-18 04:14:50 -07:00
c0496fab29 regression: disable build that times out on Travis 2017-01-19 19:07:59 -08:00
e03ba637f4 [regression] remove FancyMemTest (timing out) 2017-01-19 17:48:04 -08:00
e22b01a6fa jtag_dtm: Update regression to run and pass. 2017-01-18 12:08:13 -08:00
74b6a8d02b Refactor Tile to use cake pattern (#502)
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
c981f8b4f3 More travis job re-balancing (#481)
* [travis] Depend on pre-built docker images rather than travis cache
2016-12-11 22:02:46 -08:00
86065e5fb8 Merge remote-tracking branch 'origin/master' into bump-submodules 2016-11-28 13:49:59 -08:00
6aeadc4551 regression: disable ComparatorL2Config for now
This tests atomics against the L2.  However, we don't have an L2 yet so this
is hitting the broadcast hub, which does not support these operations.
2016-11-23 20:53:36 -08:00
837d207064 [travis] split up groundtest into two suites 2016-11-23 12:27:40 -08:00
cf8ecbd53b travis: balance regression tasks a bit more fairly 2016-11-23 10:28:22 -08:00
e8e95d4bcf regression: remove cde submodule update 2016-11-23 10:28:22 -08:00
3d1a7bd6d3 travis: build verilator and toolchain as part of install 2016-11-21 21:13:26 -08:00
ea3ec89676 travis: split RocketSuite into three smaller tests suites 2016-11-21 21:13:23 -08:00
e68795421a remove L2 regressions for now 2016-11-19 20:11:20 -08:00
fc4d6ed0c6 jtag: clean up debug flags in regression/Makefile 2016-09-29 13:49:21 -07:00
45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec 2016-09-29 13:49:14 -07:00
449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! 2016-09-29 13:48:55 -07:00
7bca99a27a [tilelink2] Add unit test configs to regression 2016-09-28 18:02:04 -07:00
77a0f76289 Cleanup jtag dtm (#342)
* debug: Clean up Debug TransportModule synchronizer

With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.

I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
2016-09-26 11:10:27 -07:00
91aab2fabc no commas in yml 2016-09-22 17:28:34 -07:00
83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
888f6a2a55 Revert "move UnitTest back into rocketchip module"
This reverts commit f95b8c4ec2.
2016-09-15 11:48:09 -07:00
f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
97809b183f refactor unittest framework
as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
67467c65f5 Add a jtag-dtm-regression target to the regression
This doesn't get added to Travis, but this target can be used
by other automated testing tools which may want to do further
testing on rocket-chip.
2016-08-23 16:53:50 -07:00
1c5034707b fix submodules in regression makefile 2016-08-19 13:45:23 -07:00
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
163cba6a85 make sure all regressions actually run 2016-08-10 14:52:06 -07:00
2906c75167 Remove fsim, as it is the same as vsim, modulo CONFIG 2016-08-09 15:42:22 -07:00
63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
39ec927a3f replace complicated pattern substitutions with automatic variable 2016-06-28 18:30:11 -07:00