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Combine Coreplex and System Module Hierarchies (#875)

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* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
This commit is contained in:
Henry Cook
2017-07-23 08:31:04 -07:00
committed by Yunsup Lee
parent f2002839eb
commit 01ca3efc2b
59 changed files with 1536 additions and 1632 deletions
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6
regression/Makefile
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@ -42,17 +42,17 @@ $(error Set SUITE to the regression suite you want to run)
endif
ifeq ($(SUITE),RocketSuiteA)
PROJECT=freechips.rocketchip.chip
PROJECT=freechips.rocketchip.system
CONFIGS=DefaultConfig
endif
ifeq ($(SUITE),RocketSuiteB)
PROJECT=freechips.rocketchip.chip
PROJECT=freechips.rocketchip.system
CONFIGS=DefaultBufferlessConfig
endif
ifeq ($(SUITE),RocketSuiteC)
PROJECT=freechips.rocketchip.chip
PROJECT=freechips.rocketchip.system
CONFIGS=TinyConfig
endif