Commit Graph
9 Commits
Author SHA1 Message Date
Scott Johnson a919a280e8 Fix Cadence Incisive compile errors; VCD-Plus is a VCS-only format
This fixes the following compile warnings and simulation errors:

Compile-time warnings:
      $vcdplusfile(vcdplusfile);
                 |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): Unrecognized system task or function: $vcdplusfile (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdpluson(0);
               |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): Unrecognized system task or function: $vcdpluson (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdplusmemon(0);
                  |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): Unrecognized system task or function: $vcdplusmemon (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
        `VCDPLUSCLOSE
                    |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): Unrecognized system task or function: $vcdplusclose (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].

Which then become simulation-time errors:

      $vcdplusfile(vcdplusfile);
                 |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): User Defined system task or function ($vcdplusfile) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdpluson(0);
               |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): User Defined system task or function ($vcdpluson) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdplusmemon(0);
                  |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): User Defined system task or function ($vcdplusmemon) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,97|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
2016-10-19 13:26:31 -07:00
Scott Johnson 9f0fda01b3 Fix Cadence Incisive compile warning
The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."

This fixes the following compile warning:

    rand_value = $random($urandom);
                       |
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
2016-10-19 13:23:36 -07:00
Scott JohnsonandGitHub f069052969 Merge pull request #403 from ucb-bar/fix-incisive-warning
Fix Verilog compile warning from Cadence Incisive
2016-10-18 10:48:32 -07:00
Scott Johnson dc4c375c7f Silence Verilog compile warning from Cadence Incisive 2016-10-17 15:44:24 -07:00
Scott Johnson 96e2cefb34 Merge branch 'master' into HEAD 2016-08-22 11:37:30 -07:00
Scott Johnson 96a868d388 enable the TestDriver to be used in a SystemVerilog UVM-based testbench, which has its own way to manage end-of-simulation and does not like anyone else to call $finish 2016-08-19 17:14:54 -07:00
Scott Johnson 2d12f6689c make CLOCK_PERIOD actually be the clock period, instead of half of the clock period 2016-08-19 16:55:57 -07:00
Scott Johnson 4dbcc568dc reorder code to get rid of messy -1 2016-08-19 16:55:57 -07:00
Scott Johnson f945acf712 rm race condition on trace_count 2016-08-19 16:55:57 -07:00