Megan Wachs
7014263c29
Update LICENSE.SiFive ( #618 )
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Bump the year for the SiFive license
2017-03-27 14:55:28 -07:00
Megan Wachs
70fa10fc55
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset ( #615 )
2017-03-27 03:29:07 -07:00
Megan Wachs
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
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* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
Wesley W. Terpstra
722b0d521f
bootrom: also setup SBI a0+a1 for when we hang ( #617 )
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This way a program started by the debugger still has the DTB handy.
2017-03-27 00:01:05 -07:00
Megan Wachs
11507ac7d6
TLROM: Use Resource as a parameter rather than assuming SimpleDevice.
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This allows more flexibility e.g. considering the ROM as part of other
devices.
2017-03-26 20:58:14 -07:00
Megan Wachs
bf648514e3
TLROM: allow name and compatibility strings to be provided by subclasses.
2017-03-26 20:58:14 -07:00
Megan Wachs
8e6beb80be
Add ucb-art/chisel-jtag ( #612 )
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* jtag: Add ucb-art/chisel-jtag to junctions.
* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch
* jtag: move to a top-level package
2017-03-26 18:03:21 -07:00
Andrew Waterman
0e2b780089
Bump hardfloat, giving us the 5th rounding mode finally!
2017-03-26 14:20:16 -07:00
Andrew Waterman
e710e32f10
Implement new FP encoding proposal
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Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
2017-03-26 14:20:16 -07:00
Andrew Waterman
7180352067
Fix groundtest to provide missing signals to TLB
2017-03-26 14:20:16 -07:00
Andrew Waterman
5d1165c850
Express PMP mask generator using a carry chain
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This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
2017-03-26 14:20:16 -07:00
Andrew Waterman
bb42f3bf3b
WIP on FPU subword recoding
2017-03-26 14:20:16 -07:00
Wesley W. Terpstra
986e1754be
Merge pull request #611 from ucb-bar/expose-back-side-bus
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rename l2FrontendBus as fsb, expose bsb
2017-03-24 23:32:50 -07:00
Wesley W. Terpstra
537274b645
coreplex: move buffers inside the coreplex
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This should make hierarchical place and route easier.
2017-03-24 22:54:48 -07:00
Yunsup Lee
5bbb75e078
rename l2FrontendBus as fsb, expose bsb
2017-03-24 22:54:48 -07:00
Henry Cook
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
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Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
Wesley W. Terpstra
19485a9861
Merge pull request #609 from ucb-bar/dtb-rom
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DTB in the bootrom
2017-03-24 21:54:13 -07:00
Wesley W. Terpstra
e74226564c
travis: add dependency on device-tree-compiler
2017-03-24 20:59:33 -07:00
Wesley W. Terpstra
f36b1766f8
TLROM: use the smallest ROM implementation that works
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The contents everywhere else are still zero.
2017-03-24 20:40:28 -07:00
Wesley W. Terpstra
ac205ca10a
bootrom: move to 0x10000 for more space (DTB on multicore is big)
2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
34f8ce653a
bootrom: follow SBI (a0=hartid, a1=dtb)
2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
9a2f0d01a1
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
Andrew Waterman
17b1ee3037
Default to 8 PMPs; support 0 PMPs
2017-03-24 16:39:52 -07:00
Andrew Waterman
97006ab396
Don't modulate PMP privilege on passsthrough when !usingVM
2017-03-24 16:39:52 -07:00
Andrew Waterman
3f0d2fe826
Instantiate PTW unconditionally
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This keeps the PMP datapaths intact. The PTW itself will get optimized
away for the !usingVM case.
2017-03-24 16:39:52 -07:00
Andrew Waterman
30415215b8
Don't check for exceptions on ScratchpadSlavePort accesses
2017-03-24 16:39:52 -07:00
Andrew Waterman
ccd5bc9a91
Improve QoR of PMP homogeneity checker
2017-03-24 16:39:52 -07:00
Andrew Waterman
0182b6ca07
bump tools
2017-03-24 16:39:52 -07:00
Andrew Waterman
e9cadf29d2
Improve DCache MMIO QoR
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No need to store the cmd field. From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
2017-03-24 16:39:52 -07:00
Andrew Waterman
fb6498f2c3
Use Reg(Vec) instead of Seq(Reg) for DCache MMIO
2017-03-24 16:39:52 -07:00
Andrew Waterman
0538dc77ce
For D$, use source 0 through N-1 for MMIO, not 1 through N
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This makes the code a bit cleaner.
2017-03-24 16:39:52 -07:00
Andrew Waterman
3951e57789
Force each TLB entry into its own clock-gate group
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This ameliorates a PMP critical path.
I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
Andrew Waterman
8d7f1d777e
Fix an embarrassing typo in the PMPHeterogeneityChecker
2017-03-24 16:39:52 -07:00
Andrew Waterman
10c39cb8d6
Disable mprv in D-mode
2017-03-24 16:39:52 -07:00
Andrew Waterman
d3bda9574c
Put page homogeneity checker in PMP
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Avoids redundancy between ITLB and DTLB
2017-03-24 16:39:52 -07:00
Andrew Waterman
9e05200e51
Don't require that PMP ranges be aligned to access size
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e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
2017-03-24 16:39:52 -07:00
Andrew Waterman
29e67279ba
add comments
2017-03-24 16:39:52 -07:00
Andrew Waterman
4c8be13a4d
Improve homogeneity circuit QoR
2017-03-24 16:39:52 -07:00
Andrew Waterman
59d6afa132
mideleg/medeleg not present without less-privileged traps
2017-03-24 16:39:52 -07:00
Andrew Waterman
38808f55d5
Share PMP mask gen between I$ and D$
2017-03-24 16:39:52 -07:00
Andrew Waterman
86d84959cf
More WIP on PMP
2017-03-24 16:39:52 -07:00
Andrew Waterman
2888779422
Flush pipeline from WB stage, not MEM
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Fixes sptbr write -> instruction translation hazard.
2017-03-24 16:39:52 -07:00
Andrew Waterman
44ca3b60ab
Retime PTW response valid bits
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It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
2017-03-24 16:39:52 -07:00
Andrew Waterman
a03556220c
Default TLB size = 32
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@davidbiancolin
2017-03-24 16:39:52 -07:00
Andrew Waterman
1875407316
Get TLB permission checks off D$ clock gating critical path
2017-03-24 16:39:52 -07:00
Andrew Waterman
a4164348b4
Expose MXR to S-mode
2017-03-24 16:39:52 -07:00
Andrew Waterman
0380aed329
PUM -> SUM
2017-03-24 16:39:52 -07:00
Andrew Waterman
2a413e4496
Remove fruitless debug()
2017-03-24 16:39:52 -07:00
Andrew Waterman
29414f3a23
Simplify interrupt-stack discipline
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f2ed45b179
2017-03-24 16:39:52 -07:00
Andrew Waterman
723352c3e2
Mitigate some more PMP critical paths
2017-03-24 16:39:52 -07:00
