riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman b70f7683d3 Merge branch 'master' into ss-frontend 
Conflicts:
	src/main/scala/ctrl.scala
 2015-01-04 19:59:18 -08:00
Andrew Waterman 87ad1a5703 More control cleanup 2015-01-04 19:46:01 -08:00
Andrew Waterman 2aee85cb11 Flush pipeline from MEM stage 
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control.  But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
 2015-01-04 16:40:16 -08:00
Andrew Waterman 94b75c7cb1 Continue refactoring control 2015-01-04 15:32:05 -08:00
Andrew Waterman 6181de4cc9 Much refactor, so control 2015-01-03 13:34:38 -08:00