20 Commits

Author	SHA1	Message	Date
Yunsup Lee	e25d420155	Improve ChiselConfig composability; bump chisel	2014-10-06 13:43:40 -07:00
Yunsup Lee	73eac94a65	Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)	2014-10-06 13:40:35 -07:00
Henry Cook	0b5f23a209	Streamlined uncore for release	2014-10-06 13:37:15 -07:00
Adam Izraelevitz	15fb4730ec	Add BuildTile parameter for Tile ... Conflicts: rocket	2014-09-25 06:50:45 -07:00
Henry Cook	7398b00d93	dir supplied by function	2014-09-25 06:50:41 -07:00
Henry Cook	5a840c5520	support for multiple tilelink paramerterizations in same design	2014-09-25 06:50:30 -07:00
Scott Beamer	f2ca887de3	better fpga configs	2014-09-25 06:47:03 -07:00
Scott Beamer	f4e6cd75ab	turn off fpu for default fpga config. ... a larger fpga can use defaultconfig	2014-09-25 06:46:16 -07:00
Yunsup Lee	09de2e2794	compute number of outstanding misses for DRAMSideLLCNull	2014-09-12 18:09:38 -07:00
Yunsup Lee	1cfd9f5a0e	add LICENSE	2014-09-12 10:15:04 -07:00
Yunsup Lee	c98afa1fea	turn off DRAMSideLLC	2014-09-11 22:10:25 -07:00
Yunsup Lee	b5a64487eb	turn off DRAMSideLLC	2014-09-11 22:07:44 -07:00
Yunsup Lee	02c08a156f	generate consts.vh from chisel source	2014-09-10 17:14:55 -07:00
Yunsup Lee	ddfd3ce968	further generalize fpga/vlsi builds	2014-09-08 00:21:57 -07:00
Henry Cook	ae05125f29	Adjustements to top-level parameters and knobs for hwacha	2014-09-07 17:57:33 -07:00
Henry Cook	4126678c9d	Merge branch 'dse' ... Conflicts: rocket uncore	2014-09-06 06:59:14 -07:00
Henry Cook	82467313dd	merge in rocketchip changes from master	2014-09-02 13:51:57 -07:00
Henry Cook	78ab83d224	refactor fpga top/config	2014-08-28 13:07:54 -07:00
Henry Cook	bf356b9cb4	Refactor to combine fpga and vlsi tops, part 1	2014-08-24 19:30:53 -07:00
Henry Cook	a41d55b643	Final parameter refactor.	2014-08-23 01:26:03 -07:00