Colin Schmidt
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ada5439c3e
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dont use env to force caches to be the same (#754)
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2017-05-18 18:46:29 -07:00 |
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Wesley W. Terpstra
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55e8d28868
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Merge pull request #747 from freechipsproject/try-travis-stages
try using a new travis staging feature
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2017-05-18 14:14:54 -07:00 |
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Colin Schmidt
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d0c00eccb9
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caches don't transfer across sudo flag changes
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2017-05-18 11:33:23 -07:00 |
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Colin Schmidt
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617dd6fe1e
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try travis suggestion on the jvm stages
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2017-05-18 11:06:43 -07:00 |
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Jack Koenig
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08eb7b0410
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Bump firrtl for bug fixes in annotation propagation and DCE (#751)
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2017-05-18 10:54:30 -07:00 |
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Henry Cook
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991a67ac68
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Merge pull request #749 from freechipsproject/unit-test-speedup
Unit test speedup
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2017-05-17 16:28:42 -07:00 |
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Henry Cook
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733ebbce0e
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Update README.md (#748)
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2017-05-17 14:53:56 -07:00 |
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Colin Schmidt
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66d660ff60
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use YAML to condense script replication
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2017-05-17 14:41:04 -07:00 |
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Wesley W. Terpstra
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748a48f667
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unittest: balance the run times of the tests
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2017-05-17 14:02:59 -07:00 |
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Wesley W. Terpstra
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bea2489507
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unittest: make overall test duration configurable
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2017-05-17 14:02:59 -07:00 |
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Wesley W. Terpstra
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c8ba6b2feb
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unittests: accept a configurable number of transactions to run
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2017-05-17 14:02:59 -07:00 |
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Wesley W. Terpstra
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f6f40b1442
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unit tests: all should accept timeout override
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2017-05-17 14:02:59 -07:00 |
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Wesley W. Terpstra
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4acc302158
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unittest: disable XBar test from regression (covered by other tests)
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2017-05-17 14:02:59 -07:00 |
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Colin Schmidt
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0c382204d4
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give them all stages
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2017-05-17 12:38:52 -07:00 |
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Colin Schmidt
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62a54e6bdb
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inline the env matrix
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2017-05-17 12:36:49 -07:00 |
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Colin Schmidt
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2f3e22aff6
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matrix outside after jobs
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2017-05-17 12:34:11 -07:00 |
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Colin Schmidt
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f3775cbbbf
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try moving matrix into jobs
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2017-05-17 12:31:13 -07:00 |
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Henry Cook
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dfabf68d9c
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Merge pull request #746 from freechipsproject/fix-bundle-refs
diplomacy: provide connect access to edges without bundles
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2017-05-17 12:28:46 -07:00 |
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Colin Schmidt
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b7dc415522
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maybe this will order them with deploy last
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2017-05-17 12:28:01 -07:00 |
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Colin Schmidt
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b9fc169367
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try another stages organization
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2017-05-17 12:24:41 -07:00 |
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Colin Schmidt
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83a5230e91
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change install to script?
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2017-05-17 12:13:31 -07:00 |
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Colin Schmidt
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bce613ce38
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try using a new travis staging feature
The idea is to let us avoid building the tools
for each SUITE
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2017-05-17 11:58:09 -07:00 |
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Wesley W. Terpstra
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8c3736e0dc
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tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer
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2017-05-17 06:47:21 -07:00 |
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Wesley W. Terpstra
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1f2236cdb3
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diplomacy: appease Jack by removing unused 1st bundles argument
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2017-05-17 06:46:07 -07:00 |
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Wesley W. Terpstra
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f2d16d49c2
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tilelink2: don't widen TLMonitor interface unnecessarily
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2017-05-17 06:29:03 -07:00 |
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Wesley W. Terpstra
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191dad7800
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diplomacy: provide connect access to edges without bundles
Forcing the bundles to exist early can mess up module ownership.
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2017-05-17 06:29:03 -07:00 |
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Wesley W. Terpstra
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65053978dc
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Merge pull request #745 from freechipsproject/tile-xbar
Tile xbar
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2017-05-17 06:28:37 -07:00 |
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Megan Wachs
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d8996ea85f
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Empty commit to force travis
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2017-05-16 22:56:58 -07:00 |
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Henry Cook
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5f22e91a7f
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rocc: fix RoccExampleConfig
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2017-05-16 16:44:53 -07:00 |
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Henry Cook
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a19fc2549e
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tile: add tileBus xbar
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2017-05-16 16:12:01 -07:00 |
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Wesley W. Terpstra
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ad087dd18d
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Merge pull request #742 from ucb-bar/true-rational
RationalCrossing: now supporting true rational N:M crossings
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2017-05-15 15:51:35 -07:00 |
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Wesley W. Terpstra
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3e2b477c0a
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rational: adjust comments and add a case for N:M
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2017-05-14 15:16:33 -07:00 |
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Wesley W. Terpstra
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2119df5a60
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vsrc: add ClockDivider3 used to simulate unaligned clocks
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2017-05-14 15:05:55 -07:00 |
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Wesley W. Terpstra
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05e7501e7a
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build: include chiselName and give an example of using it (#738)
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2017-05-12 06:25:58 -07:00 |
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Wesley W. Terpstra
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18725a05b0
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DTS tweaks (#740)
* rocket: do not report 's' in isa string
* rocket: report the micro-architecture of the core
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2017-05-12 05:32:57 -07:00 |
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Jack Koenig
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a69fcd50dd
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Bump Firrtl to add new global DCE (#741)
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2017-05-12 00:36:49 -07:00 |
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Palmer Dabbelt
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23706113c2
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Bump riscv-tools, to get some -mcmodel=medany fixes (#739)
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2017-05-11 21:04:32 -07:00 |
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Henry Cook
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5f3a4ada1b
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diplomacy: add legalize method to AddressSet
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2017-05-10 12:54:24 -07:00 |
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Henry Cook
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3af40bff8b
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tilelink: better address masking for fuzzing
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2017-05-10 12:54:24 -07:00 |
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Wesley W. Terpstra
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9720a53eae
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Merge pull request #735 from ucb-bar/early-ack-frag-fix
tilelink2: keep earlyAck Fragmenter sources distinct
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2017-05-09 18:22:59 -07:00 |
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Wesley W. Terpstra
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3eaa973da7
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tilelink2: add earlyAck to regression
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2017-05-09 17:35:26 -07:00 |
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Wesley W. Terpstra
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3e7bdcbf5e
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tilelink2: Fragmenter should ignore error when not valid
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2017-05-09 17:35:26 -07:00 |
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Wesley W. Terpstra
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43c9f5fe7e
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tilelink2: keep earlyAck Fragmenter sources distinct
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2017-05-09 17:35:22 -07:00 |
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Palmer Dabbelt
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19db0389b6
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Merge pull request #732 from ucb-bar/vectored-stvec
Support vectored stvec interrupts, too
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2017-05-09 09:34:47 -07:00 |
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Andrew Waterman
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3a9bbd7e58
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Merge branch 'master' into vectored-stvec
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2017-05-08 14:08:09 -07:00 |
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Wesley W. Terpstra
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fd76f45f65
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Merge pull request #731 from ucb-bar/axi-zero-width
axi4: Support AXI4-Lite properly
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2017-05-08 10:48:32 -07:00 |
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Wesley W. Terpstra
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2d8a49cc06
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tilelink2: Fragmenter client must request global FIFO
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2017-05-08 00:56:45 -07:00 |
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Wesley W. Terpstra
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36f4584bb1
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axi4: Test AXI4-Lite in regression
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2017-05-08 00:31:35 -07:00 |
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Wesley W. Terpstra
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3209e58845
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axi4: SRAM support 0 userBits
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2017-05-08 00:31:14 -07:00 |
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Wesley W. Terpstra
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db76ff2d86
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axi4: Deinterleaver must gather R also for single ID
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
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2017-05-08 00:17:06 -07:00 |
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