Henry Cook
9fe35382ea
sbus: tile adapters in sbus scope
2017-10-26 13:04:32 -07:00
Henry Cook
95a2e6ef27
coreplex: improve tile attachment adapters
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
2175758050
interrupts: implement in crossing wrapper
2017-10-26 13:04:29 -07:00
Wesley W. Terpstra
c6f95570df
IntNodes: moved from tilelink to their own package
2017-10-25 16:56:51 -07:00
Wesley W. Terpstra
6bc9c9fc6c
coreplex: add a crossing wrapper to generalize the island pattern
2017-10-25 16:56:50 -07:00
Wesley W. Terpstra
7453186b59
diplomacy: add reflection for parent modules to nodes
2017-10-25 16:56:50 -07:00
Christopher Celio
c4978712c9
csr: allow for superscalar decode ( #1069 )
...
* CSR provides a decode port to check for an illegal instruction.
* This commit now allows for multiple instructions in decode to get this
illegal instruction information.
* This commit leverages the existing decodeWidth parameter. This will
potentially over-provision the number of decode ports needed for
RVC-enabled cores.
Closes #1068
2017-10-25 13:58:26 -07:00
Megan Wachs
897b686377
Merge pull request #1066 from freechipsproject/diplomacy_paper
...
Add link to Diplomatic Design Patterns Paper
2017-10-23 16:52:01 -07:00
Megan Wachs
ffffafc7c3
Add link to Diplomatic Design Patterns Paper
2017-10-23 15:21:46 -07:00
Richard Xia
680f3b1620
Merge pull request #1060 from freechipsproject/fix-address-format
...
Fix address format
2017-10-19 10:45:03 -07:00
Wesley W. Terpstra
82b1aa8116
coreplex: print the A first to look nicer
2017-10-18 16:52:35 -07:00
Wesley W. Terpstra
a1ac23d7ec
coreplex: continue to print the device name in the address map
2017-10-18 16:44:53 -07:00
Richard Xia
3b36dda9e1
Merge pull request #1059 from freechipsproject/add-supports-atomics-property
...
Add atomics support to DTS JSON file.
2017-10-18 16:30:24 -07:00
Richard Xia
5a951799aa
Add atomics support to DTS JSON file.
2017-10-18 15:17:53 -07:00
Megan Wachs
e9e05b5f3b
Add a check that MaxHartIdBits is enough for all hartids ( #1054 )
...
* Add a check that MaxHartIdBits is enough for all hartids
* Correct off-by-one error in hartid check
2017-10-13 15:20:35 -07:00
Henry Cook
1852ccd8f3
Merge pull request #1053 from freechipsproject/resource-cacheable
...
tilelink: cacheable resource permission
2017-10-12 17:49:49 -07:00
Wesley W. Terpstra
8b58327fa4
axi4: conversion from TL does not need beatBytes ( #1051 )
...
We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
2017-10-12 16:41:54 -07:00
Andrew Waterman
21b5367259
Expand C.UNIMP correctly ( #1052 )
...
It was expanding to AMOADD.W, which is clearly not an illegal instruction.
2017-10-12 14:00:14 -07:00
Henry Cook
ad243ef9f5
tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so
2017-10-12 13:49:40 -07:00
Henry Cook
ad543e5bb6
Merge pull request #1050 from freechipsproject/uncacheable-tims
...
rocket: TIMs should never be cached
2017-10-12 13:04:00 -07:00
Wesley W. Terpstra
f82e441426
axi4: implement a diplomatic AXI4 clock crossing ( #1049 )
2017-10-12 00:05:45 -07:00
Henry Cook
66e4bfc2d9
rocket: TIMs should never be cached
2017-10-11 18:22:52 -07:00
Henry Cook
b64609bfe8
Merge pull request #1039 from freechipsproject/tile-crossing-params
...
Improvements wrt connecting RocketTiles to SystemBus
2017-10-11 17:12:03 -07:00
Henry Cook
024ccd8ac2
Merge pull request #1048 from freechipsproject/local_int_hookup
...
Correctly hook up the Local Interrupts into the Coreplex.
2017-10-11 17:08:24 -07:00
Megan Wachs
7b4c48d005
Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars
2017-10-11 15:10:50 -07:00
Henry Cook
60934ac622
coreplex: TilePortParams use BasicBusBlockers
2017-10-11 13:36:46 -07:00
Henry Cook
2dbe882e58
tilelink: add BasicBusBlocker device
2017-10-11 13:36:42 -07:00
Henry Cook
9f8e3d8879
tilelink: BusBypass can be sent to DeadlockDevice
2017-10-11 12:45:36 -07:00
Henry Cook
ec056535dc
tilelink: add DeadlockDevice
2017-10-11 12:44:23 -07:00
Wesley W. Terpstra
b566ffedea
system: fix DefaultFPGAConfig ( #1047 )
...
It was missing cores. Fixes #736 .
2017-10-11 10:48:41 -07:00
Wesley W. Terpstra
8e1a002c4e
Merge pull request #1033 from freechipsproject/dont-touch
...
Use chisel3.experimental.dontTouch (take 2)
2017-10-11 00:59:37 -07:00
Henry Cook
329a5c35d4
tilelink: unsafe cache cork discards outer d.sink
2017-10-11 00:30:51 -07:00
Henry Cook
1240cb275c
coreplex: TilePortParams formatting
2017-10-11 00:29:11 -07:00
Wesley W. Terpstra
6f3a4cd733
build: pass annotations to firrtl
2017-10-10 23:42:55 -07:00
Wesley W. Terpstra
5d62c321f4
generator: create annotation file
2017-10-10 23:23:06 -07:00
Henry Cook
75345b6048
rocket: don't remove ports on top module
2017-10-10 21:28:59 -07:00
Wesley W. Terpstra
5ff4c1674a
Merge pull request #1044 from freechipsproject/nicer-clint
...
clint: use RegField.toBytes to save some work
2017-10-10 20:33:00 -07:00
Wesley W. Terpstra
b3bdf5eca6
RegField: default argument for .bytes
2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
e094b94ce5
clint: use RegField.toBytes to save some work
2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
10472b4296
diplomacy: auto connect bundles in a stable order ( #1045 )
2017-10-10 19:41:46 -07:00
Henry Cook
1867a5b226
rocket: only cache when AcquireT is possible
2017-10-10 18:06:58 -07:00
Andrew Waterman
b2bc46471b
Conditionalize some covers that are sometimes impossible ( #1043 )
2017-10-10 17:14:33 -07:00
Richard Xia
ef28ce8d2f
Merge pull request #1042 from freechipsproject/bump-riscv-tools
...
Bump riscv-tools.
2017-10-10 16:31:38 -07:00
Henry Cook
37406706b4
coreplex: move CacheCork in front of SBus
...
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
2017-10-10 16:24:32 -07:00
Henry Cook
8f5f80f958
coreplex: TileSlavePortParams inject adapters into PBus
2017-10-10 15:25:08 -07:00
Henry Cook
660355004e
coreplex: TileMasterPortParams inject adapters into SBus
2017-10-10 15:02:50 -07:00
Richard Xia
167aa7b793
Bump riscv-tools.
2017-10-10 14:14:10 -07:00
Andrew Waterman
50429daef4
Merge pull request #1036 from freechipsproject/l1-cover
...
Add some covers for L1 memory system
2017-10-10 12:28:48 -07:00
Henry Cook
9026646459
coreplex: first cut at using RocketCrossingParams
2017-10-10 12:02:04 -07:00
Wesley W. Terpstra
d6766a8c68
RocketTile: make sure 'hartid' is available for traits ( #1037 )
2017-10-09 21:03:18 -07:00