Scott Johnson
9f0fda01b3
Fix Cadence Incisive compile warning
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The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."
This fixes the following compile warning:
rand_value = $random($urandom);
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ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
2016-10-19 13:23:36 -07:00
Scott Johnson and GitHub
f069052969
Merge pull request #403 from ucb-bar/fix-incisive-warning
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Fix Verilog compile warning from Cadence Incisive
2016-10-18 10:48:32 -07:00
Scott Johnson
dc4c375c7f
Silence Verilog compile warning from Cadence Incisive
2016-10-17 15:44:24 -07:00
Scott Johnson
96e2cefb34
Merge branch 'master' into HEAD
2016-08-22 11:37:30 -07:00
Scott Johnson
96a868d388
enable the TestDriver to be used in a SystemVerilog UVM-based testbench, which has its own way to manage end-of-simulation and does not like anyone else to call $finish
2016-08-19 17:14:54 -07:00
Scott Johnson
2d12f6689c
make CLOCK_PERIOD actually be the clock period, instead of half of the clock period
2016-08-19 16:55:57 -07:00
Scott Johnson
4dbcc568dc
reorder code to get rid of messy -1
2016-08-19 16:55:57 -07:00
Scott Johnson
f945acf712
rm race condition on trace_count
2016-08-19 16:55:57 -07:00
Scott Johnson
