riscv/rocket-chip
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Author SHA1 Message Date
Rimas Avizienis 7a528d6255 fixes for div/mul hazard checking + cleanup 2011-11-01 23:14:34 -07:00
Rimas Avizienis d8ffecf565 dcache fix 2011-11-01 22:10:06 -07:00
Rimas Avizienis 7479e085ec dcache loads working - 1/2 cycle load/use delay depending on load type 2011-11-01 22:04:45 -07:00
Rimas Avizienis 3b3d988fde dcache loads working - 1/2 cycle load/use delay depending on load type 2011-11-01 21:25:52 -07:00
Rimas Avizienis 2b67eee683 pipeline changes for replay on dcache miss 2011-11-01 19:05:27 -07:00
Rimas Avizienis 08b89e7710 interface cleanup, major pipeline changes 2011-11-01 17:59:27 -07:00
Rimas Avizienis ace4c9d13c dcache fixes 2011-10-31 17:17:36 -07:00
Rimas Avizienis 65f8b2461c dcache tweaks 2011-10-31 16:47:31 -07:00
Rimas Avizienis 172e561a78 added once cycle latency store pipelined d$ 2011-10-31 15:37:37 -07:00
Rimas Avizienis c06e2d16e4 initial commit of rocket chisel project, riscv assembly tests and benchmarks 2011-10-25 23:02:47 -07:00