Andrew Waterman
8e63f4a1a5
Remove ClockToSignal and vice-versa
...
Clock.asUInt and Bool.asClock now suffice.
2016-09-21 16:17:14 -07:00
Yunsup Lee
1b26d78114
correctly print out the addrmap overlapping error message
2016-09-19 13:34:58 -07:00
Wesley W. Terpstra
fb24e847fd
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
Henry Cook
0a65238920
Merge branch 'master' into tl2-irrevocable
2016-09-15 10:30:50 -07:00
Howard Mao
646527c88e
use named constants to set AXI resp, cache, and prot fields
2016-09-14 21:16:54 -07:00
Henry Cook
cde104b3fa
[junctions] Removes the obsoleted SMI.
...
Closes #280 .
2016-09-14 20:06:22 -07:00
Henry Cook
d35060b881
[junctions] messed up the merge lulz
2016-09-14 17:55:16 -07:00
Henry Cook
1b53e477fa
Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
2016-09-14 17:50:17 -07:00
Henry Cook
08c4c7b985
[junctions] make async crossings capable of providing IrrevocableIO
2016-09-14 17:38:54 -07:00
Megan Wachs
1308680f75
Add some async/clock utilities
2016-09-14 16:30:59 -07:00
Andrew Waterman
5828e6042e
Work around https://github.com/ucb-bar/firrtl/issues/299
2016-09-14 11:47:10 -07:00
Howard Mao
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb
First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
cc88bf1b08
junctions: give unit tests more time
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
44501cdbf8
crossings: change defaults to sync=3 for safer settling time
...
Make the matching AsyncQueue depth=8 to support full throughput
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
3348236320
junctions: remove obsolete Handshaker crossing
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
d75f9d6a34
junctions: add an AsyncQueue
2016-09-13 17:38:18 -07:00
Wesley W. Terpstra
8142406d2e
junctions: refactor the Crossing type
2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5
crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain
2016-09-13 15:51:18 -07:00
Henry Cook
05100c12a7
Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor
2016-09-13 11:18:18 -07:00
Wesley W. Terpstra
606f19a17f
tilelink2: RegisterRouter Unit Test
2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
273d3a73f2
tilelink2: Unit Test passes!
2016-09-12 18:39:50 -07:00
Henry Cook
0671d5d637
Initial version of fuzzer and simple ram fuzz test
2016-09-12 10:32:45 -07:00
Yunsup Lee
bb3f514e8d
now able to add periphery devices through traits
...
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
2016-09-10 23:39:29 -07:00
Yunsup Lee
e35e7b2ee3
Fix routing in non-contiguous MMIO regions
...
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
2016-09-07 19:28:12 -07:00
Yunsup Lee
b76612f357
relax contraint on adding AddrMapEntry to AddrMap ( #248 )
...
now you can add them in any order. there's an explicit check at the end to figure out whether there are overlapping regions.
2016-09-06 21:53:55 -07:00
Howard Mao
66de89c4db
allow fixed priority routing in Junctions arbiters
2016-09-04 10:55:19 -07:00
Howard Mao
efe8670283
allow Serializer/Deserializer to work with arbitrary Chisel data types
2016-09-04 10:55:19 -07:00
Howard Mao
b9b79e4fb6
get rid of AtoS RTL
2016-09-04 10:55:19 -07:00
Yunsup Lee
4a7972be31
connect testharness components via member functions ( #236 )
...
to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
Megan Wachs
75efc7dee7
JtagIO's DRV_TDO should be an INPUT
2016-08-19 16:38:03 -07:00
Megan Wachs
723cc063cb
Move files after the file reorganization
2016-08-19 16:11:41 -07:00
Howard Mao
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
