Palmer Dabbelt
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3bb0f11e6c
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Chisel3 <> reverse fix
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2016-02-05 09:56:42 -08:00 |
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Henry Cook
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9769b2747c
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now depend on external cde library rather than chisel.params (bump all submodules)
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2015-10-21 18:24:16 -07:00 |
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Henry Cook
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1c489d75c1
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inject params at top-level for MemDessert
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2015-10-06 16:26:58 -07:00 |
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Henry Cook
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c4eadbda57
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Removed all traces of params
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2015-10-06 11:42:06 -07:00 |
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Henry Cook
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38ae2707a3
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refactor MemIO to not use params
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2015-10-06 11:41:48 -07:00 |
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Henry Cook
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3d10a89907
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refactor NASTI to not use param; new AddrMap class
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2015-10-06 11:41:47 -07:00 |
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Howard Mao
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8d4d8680bf
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replace NASTIMasterIO and NASTISlaveIO with NASTIIO
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2015-09-24 16:59:13 -07:00 |
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Howard Mao
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56ecdff52d
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Implement NASTI-based Mem/IO interconnect
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2015-09-22 10:32:31 -07:00 |
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Andrew Waterman
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34b9a7fdc5
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Various Chisel3 compatibility changes
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2015-08-03 18:54:56 -07:00 |
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Henry Cook
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51c42083d0
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Add new junctions repo as submodule (contains externally facing buses and peripherals).
Bump all submodules.
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2015-07-29 18:15:45 -07:00 |
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Henry Cook
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d3ccec1044
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Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Henry Cook
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122733b3a9
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file name consistency
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2014-10-06 13:37:38 -07:00 |
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