  Palmer DabbeltandAndrew Waterman
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25ade44fe3
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Don't build the Verilator man pages (#141)
These failed for Andrew earlier. While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.
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2016-06-16 10:13:21 -07:00 |
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Palmer DabbeltandAndrew Waterman
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82cef6fa7b
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Make a TileLink to Smi converter availiable to users (#136)
See the cooresponding uncore commit for details.
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2016-06-10 18:49:17 -07:00 |
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Palmer Dabbelt
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7c33d88861
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Merge pull request #90 from ucb-bar/elaborate-once
Bump Chisel3, to elaborate circuits once
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2016-04-18 21:04:55 -07:00 |
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Palmer Dabbelt
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85c86994a0
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Bump Chisel3, to elaborate circuits once
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2016-04-18 14:54:17 -07:00 |
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Palmer Dabbelt
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7d5eac189b
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Bump the uncore for some Chisel3 fixes
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2016-03-24 12:00:13 -07:00 |
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Palmer Dabbelt
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7fa38b5624
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Merge pull request #68 from ucb-bar/test-and-fix-backup-mem
Fix the backup memory port
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2016-02-27 12:19:55 -08:00 |
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Palmer Dabbelt
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90a73c621d
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Merge pull request #58 from ucb-bar/more-travis-fixing
More travis fixing
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2016-02-23 21:26:16 -08:00 |
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Palmer Dabbelt
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700d756de0
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Merge pull request #55 from ucb-bar/travis-regression
travis-ci.org improvements
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2016-02-23 12:19:59 -08:00 |
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Palmer Dabbelt
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0ac5c07683
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Merge pull request #54 from ucb-bar/fsim-no-htif
The FPGA doesn't have an HTIF clock divider
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2016-02-22 20:02:03 -08:00 |
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Palmer Dabbelt
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96b77f399c
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Merge pull request #43 from ucb-bar/chisel3
Bump junctions, for a chisel3 fix
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2016-02-08 14:42:06 -08:00 |
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Palmer Dabbelt
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97640f099d
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Merge pull request #41 from ucb-bar/regressions
Support torture regressions
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2016-02-01 18:39:28 -08:00 |
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