Andrew Waterman
6176b348dc
Invalidate TL error bit in D$ once progress is made
2017-11-07 00:52:18 -08:00
Andrew Waterman
d8d4504995
Provide separate masks for local & global BusErrorUnit interrupts
2017-11-06 18:03:59 -08:00
Andrew Waterman
be3a3e0187
Generate local interrupt #128 on bus errors
...
It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
2017-11-06 18:03:59 -08:00
Andrew Waterman
ac096a89e7
Make BusErrorUnit support 32-bit stores
...
Otherwise it isn't too useful for RV32!
2017-11-06 18:03:59 -08:00
Andrew Waterman
6357db0b12
Expose BusErrorUnit non-diplomatically for use as local interrupt
2017-11-06 18:03:59 -08:00
Andrew Waterman
bdda2cb145
Merge pull request #1089 from freechipsproject/aswaterman-patch-1
...
Don't emit PTW covers when !usingVM
2017-11-06 18:03:36 -08:00
Andrew Waterman
95d00b13cc
Report ITIM slave port errors to BusErrorUnit
2017-11-06 12:39:17 -08:00
Andrew Waterman
c84848afa6
Report ITIM uncorrectable errors over D-channel
2017-11-06 12:32:45 -08:00
Andrew Waterman
989eeb78f9
Prevent some unnecessary pipeline replays
2017-11-06 11:04:06 -08:00
Andrew Waterman
c8bc487ab8
Use pseudo-LRU policy in BTB
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FIFO falls on its face if the working set doesn't fit in the BTB.
2017-11-03 16:27:04 -07:00
Andrew Waterman
f859da85ff
Disable covers that don't apply to DTIM
2017-11-03 15:38:13 -07:00
Andrew Waterman
d6ede818ee
DTIM doesn't accept grants
2017-11-03 15:37:48 -07:00
Andrew Waterman
7bef935d2a
Don't emit PTW covers when !usingVM
2017-11-03 15:03:27 -07:00
Andrew Waterman
3db066303b
Fix ITIM bug overwriting I$ contents when deallocating ITIM ( #1079 )
...
Workaround: disable interrupts and then do:
.align 3
sb x0, (t0) # t0 contains ITIM-deallocate address
fence.i
2017-10-31 00:49:56 -07:00
Wesley W. Terpstra
a954f020a9
diplomacy: use new node style chaining
2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
9f83db998e
tile: don't chain too many unneeded TileLink adapters ( #1075 )
2017-10-27 01:12:58 -07:00
Wesley W. Terpstra
c6f95570df
IntNodes: moved from tilelink to their own package
2017-10-25 16:56:51 -07:00
Christopher Celio
c4978712c9
csr: allow for superscalar decode ( #1069 )
...
* CSR provides a decode port to check for an illegal instruction.
* This commit now allows for multiple instructions in decode to get this
illegal instruction information.
* This commit leverages the existing decodeWidth parameter. This will
potentially over-provision the number of decode ports needed for
RVC-enabled cores.
Closes #1068
2017-10-25 13:58:26 -07:00
Andrew Waterman
21b5367259
Expand C.UNIMP correctly ( #1052 )
...
It was expanding to AMOADD.W, which is clearly not an illegal instruction.
2017-10-12 14:00:14 -07:00
Henry Cook
66e4bfc2d9
rocket: TIMs should never be cached
2017-10-11 18:22:52 -07:00
Henry Cook
b64609bfe8
Merge pull request #1039 from freechipsproject/tile-crossing-params
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Improvements wrt connecting RocketTiles to SystemBus
2017-10-11 17:12:03 -07:00
Henry Cook
1867a5b226
rocket: only cache when AcquireT is possible
2017-10-10 18:06:58 -07:00
Andrew Waterman
b2bc46471b
Conditionalize some covers that are sometimes impossible ( #1043 )
2017-10-10 17:14:33 -07:00
Henry Cook
9026646459
coreplex: first cut at using RocketCrossingParams
2017-10-10 12:02:04 -07:00
Andrew Waterman
1474ab438d
Remove extraneous signal
2017-10-09 18:33:50 -07:00
Andrew Waterman
f3825270c1
Add some covers for L1 memory system
2017-10-09 18:33:36 -07:00
Andrew Waterman
986cbfb6b1
For Rockets without VM, widen vaddrBits to paddrBits
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This supports addressing a >39-bit physical address space.
2017-10-08 01:21:47 -07:00
Andrew Waterman
a0e5a20b60
Don't route branch comparison result through ALU output mux
...
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
2017-10-07 17:36:24 -07:00
Wesley W. Terpstra
bd045a3b95
tilelink: split Acquire into Acquire{Block,Perm} ( #1030 )
...
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.
Instead of calling it Overwrite, we decided to split the Acquire type.
If you AcquirePerm, you MUST Release and ProbeAck with Data.
2017-10-05 12:49:49 -07:00
Henry Cook
45581e60f0
Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
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This reverts commit 5232a29d7d838ef95d33bfcd2a6fbfde8a82af35, reversing
changes made to a2dc13669a3001f5024426eda36ed4c4df8b7ceb.
2017-10-05 00:26:44 -07:00
Andrew Waterman
7bcf28c585
Define fetchBytes in HasCoreParams, not Frontend
...
It is more generally useful.
2017-10-03 17:34:18 -07:00
Andrew Waterman
2786e42d99
Don't register interrupts in CSRFile
...
They are usually registered outside the tile in a CDC.
2017-10-03 17:34:18 -07:00
Andrew Waterman
5cfe070932
Add option to make misa read-only
2017-10-03 17:34:18 -07:00
Andrew Waterman
09468a272b
Add option to remove basic counters (mcycle/minstret)
2017-10-03 17:34:18 -07:00
Andrew Waterman
ab0821f25b
Move microarchitecture-neutral params from Rocket to Core
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This makes some of the units more reusable.
2017-10-03 17:34:18 -07:00
Andrew Waterman
190d5c50d9
Remove deprecated custom-CSR support
2017-10-03 17:34:18 -07:00
Henry Cook
aa3a18222c
HellaCache: users like to peep resp.data and resp.addr
2017-10-02 19:36:30 -07:00
Andrew Waterman
9137f54f59
Merge pull request #1020 from freechipsproject/fix-trace-insn
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Provide correct trace insn on interrupts when possible
2017-09-27 18:47:24 -07:00
Andrew Waterman
9eaf50762e
Don't report exceptions as valid instructions in the printed log
2017-09-27 16:29:42 -07:00
Wesley W. Terpstra
0a287df0f7
Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles
2017-09-27 16:28:10 -07:00
Andrew Waterman
31c5246446
Provide correct trace insn on interrupts when possible
2017-09-27 16:27:53 -07:00
Henry Cook
05112b49a3
Merge branch 'master' into tl-error
2017-09-27 14:50:17 -07:00
Andrew Waterman
78f3877e02
Trace tval field should be zero when not taking exceptions
2017-09-27 12:51:10 -07:00
Andrew Waterman
583adeee88
Separate interrupt bit from cause field in trace bundle
2017-09-27 12:41:30 -07:00
Wesley W. Terpstra
5323cf88dd
util: add Option.unzip
2017-09-25 12:06:31 -07:00
Wesley W. Terpstra
60614055e3
diplomacy: eliminate some wasted IdentityNodes using cross-module refs
2017-09-25 12:06:27 -07:00
Wesley W. Terpstra
b9a2e4c243
diplomacy: API beautification
2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4
diplomacy: change API to auto-create node bundles => cross-module refs
2017-09-22 15:01:39 -07:00
Wesley W. Terpstra
dfc815f4d3
rocket: invoke LazyModule at point of use/binding
2017-09-22 14:38:47 -07:00
Henry Cook
81e136aa37
rocket: give l2 tlb a nice name
2017-09-21 18:13:39 -07:00
