Megan Wachs
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42ca597478
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debug: Breaking change until FESVR is updated as well.
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
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2017-03-27 21:19:08 -07:00 |
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Wesley W. Terpstra
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ac205ca10a
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bootrom: move to 0x10000 for more space (DTB on multicore is big)
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2017-03-24 18:18:01 -07:00 |
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Wesley W. Terpstra
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34f8ce653a
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bootrom: follow SBI (a0=hartid, a1=dtb)
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2017-03-24 18:18:01 -07:00 |
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Henry Cook
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a281ad8ad2
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rocketchip: rename some periphery ports
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2017-02-23 18:28:04 -08:00 |
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Wesley W. Terpstra
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b7963eca4e
|
copyright: ran scripts/modify-copyright
|
2016-11-27 22:15:43 -08:00 |
|
Wesley W. Terpstra
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4b9dc78951
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rocketchip: add a parameter-controlled debug port
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2016-11-23 15:35:53 -08:00 |
|
Wesley W. Terpstra
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37a3c22639
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rocketchip: move from using cde to config
|
2016-11-18 16:18:33 -08:00 |
|
Wesley W. Terpstra
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10e459fedb
|
rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
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2016-11-15 18:27:52 -08:00 |
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