129 lines
3.2 KiB
Scala
129 lines
3.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocketchip
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import Chisel._
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import config._
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import diplomacy._
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import uncore.tilelink2._
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import uncore.devices._
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import util._
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import junctions.JTAGIO
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import coreplex._
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/// Core with JTAG for debug only
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trait PeripheryJTAG extends HasTopLevelNetworks {
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val module: PeripheryJTAGModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryJTAGBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryJTAG
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val jtag = new JTAGIO(true).flip
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}
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trait PeripheryJTAGModule extends HasTopLevelNetworksModule {
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val outer: PeripheryJTAG
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val io: PeripheryJTAGBundle
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val dtm = Module (new JtagDTMWithSync)
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dtm.io.jtag <> io.jtag
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outer.coreplex.module.io.debug <> dtm.io.debug
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dtm.clock := io.jtag.TCK
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dtm.reset := io.jtag.TRST
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}
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/// Core with DTM for debug only
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trait PeripheryDTM extends HasTopLevelNetworks {
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val module: PeripheryDTMModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryDTMBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryDTM
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val debug = new DebugBusIO().flip
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}
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trait PeripheryDTMModule extends HasTopLevelNetworksModule {
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val outer: PeripheryDTM
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val io: PeripheryDTMBundle
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outer.coreplex.module.io.debug <> ToAsyncDebugBus(io.debug)
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}
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/// Core with DTM or JTAG based on a parameter
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trait PeripheryDebug extends HasTopLevelNetworks {
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val module: PeripheryDebugModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryDebugBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryDebug
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val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip)
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val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip)
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}
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trait PeripheryDebugModule extends HasTopLevelNetworksModule {
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val outer: PeripheryDebug
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val io: PeripheryDebugBundle
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io.debug.foreach { dbg => outer.coreplex.module.io.debug <> ToAsyncDebugBus(dbg) }
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io.jtag.foreach { jtag =>
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val dtm = Module (new JtagDTMWithSync)
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dtm.clock := jtag.TCK
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dtm.reset := jtag.TRST
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dtm.io.jtag <> jtag
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outer.coreplex.module.io.debug <> dtm.io.debug
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}
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}
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/// Real-time clock is based on RTCPeriod relative to Top clock
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trait PeripheryCounter extends HasTopLevelNetworks {
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val module: PeripheryCounterModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryCounterBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryCounter
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}
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trait PeripheryCounterModule extends HasTopLevelNetworksModule {
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val outer: PeripheryCounter
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val io: PeripheryCounterBundle
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{
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val period = p(rocketchip.RTCPeriod)
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val rtcCounter = RegInit(UInt(0, width = log2Up(period)))
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val rtcWrap = rtcCounter === UInt(period-1)
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rtcCounter := Mux(rtcWrap, UInt(0), rtcCounter + UInt(1))
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outer.coreplex.module.io.rtcToggle := rtcCounter(log2Up(period)-1)
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}
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}
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/// Coreplex will power-on running at 0x1000 (BootROM)
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trait HardwiredResetVector extends HasTopLevelNetworks {
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val module: HardwiredResetVectorModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait HardwiredResetVectorBundle extends HasTopLevelNetworksBundle {
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val outer: HardwiredResetVector
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}
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trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
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val outer: HardwiredResetVector
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val io: HardwiredResetVectorBundle
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outer.coreplex.module.io.resetVector := UInt(0x1040) // boot ROM: hang
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}
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