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riscv/rocket-chip
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Code Releases Activity
950 Commits 1 Branch 0 Tags
6d1bf5c014cf736f74ac8f7e261928c1b9628f46
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13 Commits
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Author SHA1 Message Date
Howard Mao b0a06a77db fix a few Chisel3 compat issues 2015-11-20 13:33:15 -08:00
Howard Mao 19daee10f0 use default constructors for IOMSHR acquire construction 2015-11-12 15:54:05 -08:00
Howard Mao 0b7c828b5d go back to using standard LockingArbiter 2015-10-21 09:15:51 -07:00
Howard Mao c68d9f8137 make ProbeUnit state machine easier to understand 2015-10-20 23:25:23 -07:00
Howard Mao 19656e4abe make sure to generate release from clean coh state on probe miss 2015-09-30 16:58:18 -07:00
Howard Mao 2f3d15675c fix DataArray writemask in L1D 2015-09-28 16:02:39 -07:00
Howard Mao 4bda6b6757 fix bug in tlb refill 2015-09-26 21:27:36 -07:00
Howard Mao 6bf8f41cef make sure passthrough requests are treated as vm_enabled = false 2015-09-26 20:29:51 -07:00
Howard Mao a66bdb1956 replace remaining uses of Vec.fill 2015-09-24 17:53:26 -07:00
Howard Mao 9eb988a4c6 make sure access to invalid physical address treated as exception 2015-09-22 10:11:43 -07:00
Howard Mao 16c748576a don't mux data_word_bypass between IOMSHR and cache 2015-09-22 10:10:57 -07:00
Howard Mao d89bcd3922 modify csr file to bring in line with HTIF changes 2015-09-22 10:10:57 -07:00
Howard Mao 382faba4a6 Implement bypassing L1 data cache for MMIO 2015-09-22 10:10:57 -07:00
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