6bc20942b5
Don't cache TL error responses; report access exceptions
2017-09-20 17:01:08 -07:00
db57e943f3
Report TL errors into D$
2017-09-20 00:05:07 -07:00
ed18acaae0
Report D$ errors
2017-09-20 00:05:07 -07:00
57e8fe0a6b
Merge pull request #1000 from freechipsproject/name-seqmems
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try to give seqmems clearer names for use with external tools
2017-09-19 17:59:00 -07:00
8db5bbbae0
try to give seqmems clearer names
2017-09-19 13:41:11 -07:00
d93d7b9fa4
Only merge stores that aren't yet pending
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This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed). The following sequence manifests it, assuming t0
is 32-byte aligned:
sw t0, 0(t0)
sw t0, 16(t0)
lw t1, 4(t0)
lw t2, 4(t0)
2017-09-17 15:01:07 -07:00
1f606d924f
Don't perform in-place correction if there was a recent store ( #988 )
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Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store. So,
re-read the word after all pending stores have drained.
2017-09-08 16:26:54 -07:00
53dfc5e9be
Remove overzealous assertion ( #987 )
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This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled. However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.
This happens when resolving a tag ECC error during hit-under-miss.
2017-09-07 18:17:56 -07:00
3cbc5262ec
Don't permit new acquires until the release queue is drained
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If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
0190724492
Actually use the C-channel acquire-before-release queue
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oops...
2017-08-13 13:03:35 -07:00
7387f2a93a
Don't block D-channel when handling a probe
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This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
604abd5b07
Only report ECC errors when the RAM was actually read
2017-08-12 15:28:03 -07:00
18fb052fc9
DRY
2017-08-12 15:27:30 -07:00
176110b6d3
Don't trigger ECC writebacks when a release is in flight
2017-08-12 15:23:57 -07:00
809c7e8551
Don't merge stores that manifest WAW hazards
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The following sequence would drop the first store when eccBytes=4:
sb x0, 0(t0)
nop
sb x0, 4(t0)
nop
sb x0, 1(t0)
Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
2017-08-08 15:19:05 -07:00
82e13443b2
Merge pull request #937 from freechipsproject/critical-paths
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Perform tag error detectoin/correction in same cycle as RAM
2017-08-08 15:03:28 -07:00
7935c61c19
Don't report to the DTIM that data is cacheable
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Otherwise, it will attempt to perform AMOs where they're unsupported!
2017-08-08 11:55:04 -07:00
74d309c18e
Make I vs. D a static property of TLB, not an input pin
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The microarchitecture doesn't really support unified TLBs, so don't fake it.
2017-08-08 11:54:47 -07:00
e92981b0bd
DRY
2017-08-08 11:46:38 -07:00
62ccba304c
Perform tag error detectoin/correction in same cycle as RAM
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The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
2017-08-08 10:21:30 -07:00
402907990c
Revert "Remove one gate from D$ ECC check"
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This reverts commit 7d94074b05
2017-08-07 17:33:20 -07:00
7d94074b05
Remove one gate from D$ ECC check
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The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
2017-08-06 17:36:53 -07:00
83875e3a0c
Only flush D$ on FENCE.I if it won't always be probed on I$ miss
2017-08-05 14:22:40 -07:00
991e16de92
Remove probe address mux from TLB response path
2017-08-05 12:57:38 -07:00
2eb239d03f
Add option to retime D$ way mux into subsequent pipeline stage
2017-08-01 23:59:20 -07:00
2ecea2ef60
Don't use a pipe queue on D$ TL A-channel
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This cuts an I$->D$ path.
2017-08-01 15:17:07 -07:00
5681693ccc
Fix a D$ ready-valid signaling regression
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I broke this in 66d06460fa
2017-07-31 18:05:14 -07:00
11332c1226
dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative
2017-07-31 14:03:30 -07:00
ac4339a8e7
Pass D$ backpressure to D-channel, rather than asserting
2017-07-29 11:48:36 -07:00
edcd2c696c
Avoid needless stall on E-channel back pressure
2017-07-29 11:47:58 -07:00
2e8b02e780
Merge D$ store hits when ECC is enabled
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This avoids pipeline flushes due to subword WAW hazards, as with
consecutive byte stores.
2017-07-28 12:56:36 -07:00
838864870e
Bypass TLB refill signal to halve L2 TLB hit time
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The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
2017-07-28 12:56:36 -07:00
ae1f7a95f6
Don't nack misses when there's a pending store
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That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss. Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
2017-07-28 12:56:36 -07:00
66d06460fa
Add option for acquire-before-release
2017-07-25 15:19:16 -07:00
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
be4eceec0d
Fix stupid D$ probe bug
2017-07-06 01:20:47 -07:00
90a7d6a343
Add L2 TLB option
2017-07-06 01:19:18 -07:00
0ef45fac9b
Add tag ECC to D$
2017-07-03 18:16:37 -07:00
e9752f76ae
Improve probe state machine
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- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
2017-07-03 16:25:04 -07:00
5b46350bc3
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 17:44:16 -07:00
ca3030cba3
dcache: fix a gender inversion bug introduced in #826
2017-06-28 15:38:53 -07:00
b9a934ae28
Support eccBytes > 1
2017-06-28 02:09:18 -07:00
6f8fdff762
Basic L1 D$ ECC support
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Only supports ECC on data, not tags; only supports byte granularity.
2017-06-28 02:09:18 -07:00
6100600179
Minor D$ code cleanup
2017-06-28 02:09:18 -07:00
8aa16a11f3
Reduce D$ access energy when refill width > access width
2017-06-28 02:09:18 -07:00
25f585f2a9
Remove unused signal from TLB interface
2017-06-28 02:09:18 -07:00
6b79842e66
dcache: just left shift by untagbits to get tag
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Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
80c63c0da6
rocket: include hartid in cache master names
2017-06-02 15:52:23 -07:00
dbc5e7c494
Add TLB miss performance counters ( #762 )
2017-05-23 12:52:25 -07:00
b2b4c1abcd
Separate tag ECC and data ECC options ( #761 )
2017-05-23 12:51:48 -07:00
