riscv/rocket-chip
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681b43f3983bc9303db0d63a65ae7f133b22f8bf
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Author SHA1 Message Date
Christopher Celio 681b43f398 Bug fixes with global history register. 
- Updated in fetch speculatively.
      * Updates gated off by cpu.resp.fire().
      * BTB direction factored into history update.
   - All branches update the BHT.
   - Each instruction carries history; index into BHT is recomputed by
     passing in mem_reg_pc.
 2014-09-26 10:39:57 -07:00
Christopher Celio a71bdbbc54 Update history register in fetch speculatively 2014-09-26 05:42:08 -07:00
Christopher Celio f917810061 Removed RocketCoreParameters from use. 
- The nbdache (among others?) use CoreParameters, which has nothing to do with RetireWidth requirements.
   - This conflicts with other cores which uses nbdcache.
   - RocketCoreParameters may be unneccessary, and the require() check can be moved deeper into Rocket.
 2014-09-26 05:14:50 -07:00
Christopher Celio 868e747656 Factored out Rocket specifics from CoreParameters 
- Added new RocketCoreParameters
   - Other cores using Rocket as a library will no longer conflict against
      Rocket's requires().
 2014-09-25 18:52:58 -07:00
Christopher Celio a2be21361e Allow ICacheConfig to toggle fetch-width. 2014-01-22 16:19:57 -08:00
Christopher Celio 1be9d15944 Fixed bug regarding case sensitivity regarding ioICache,ioDCache 2012-02-07 14:07:42 -08:00