5df8f0d1ea
Add L2 TLB miss counter
2017-07-25 15:19:16 -07:00
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
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* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
a0cbc376b4
Merge pull request #849 from freechipsproject/l2-tlb
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L1 memory system improvements
2017-07-06 13:03:06 -07:00
e1cc0a0a0e
Mask debug interrupts similarly to other interrupts ( #847 )
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This makes single-step exceptions higher-priority than debug interrupts.
2017-07-06 12:03:24 -07:00
b2351c5fbf
Use consistent casing
2017-07-06 11:16:56 -07:00
be4eceec0d
Fix stupid D$ probe bug
2017-07-06 01:20:47 -07:00
90a7d6a343
Add L2 TLB option
2017-07-06 01:19:18 -07:00
438abc76d2
Handle TL errors in L1 I$
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Cache the error bit in the tag array; report precisely on access.
2017-07-06 01:02:11 -07:00
0ef45fac9b
Add tag ECC to D$
2017-07-03 18:16:37 -07:00
e9752f76ae
Improve probe state machine
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- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
2017-07-03 16:25:04 -07:00
5b46350bc3
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 17:44:16 -07:00
5edc4546e3
rocket: add dtim and itim refs to cpus
2017-06-28 23:10:58 -07:00
7d6f8d48f2
Revert "rocket: link dtim to its cpu"
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This reverts commit e6c2d446cc
2017-06-28 23:10:57 -07:00
fbcd6f0eb2
Revert "rocket: link itim to its cpu"
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This reverts commit 48390ed604
2017-06-28 23:10:57 -07:00
6e5a4c687f
diplomacy: a type of connect that always disables monitors ( #828 )
2017-06-28 21:48:10 -07:00
992b480c74
Merge pull request #825 from freechipsproject/debug_wfi
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Debug + WFI Interactions
2017-06-28 21:28:51 -07:00
ca3030cba3
dcache: fix a gender inversion bug introduced in #826
2017-06-28 15:38:53 -07:00
48390ed604
rocket: link itim to its cpu
2017-06-28 15:06:19 -07:00
e6c2d446cc
rocket: link dtim to its cpu
2017-06-28 15:06:19 -07:00
3f6d5110cd
rocket: dtim is not a dcache
2017-06-28 15:06:19 -07:00
84dc23c215
devices: add reg-names to most devices
2017-06-28 15:06:16 -07:00
852f03282f
rocket: give itim and dtim a compatible field for drivers to match
2017-06-28 14:26:55 -07:00
b9a934ae28
Support eccBytes > 1
2017-06-28 02:09:18 -07:00
8e4be40efc
Propagate wb_reg_rs2 for sfence ASID
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This would have been a bug if we supported ASIDs.
2017-06-28 02:09:18 -07:00
2077e4190b
Make log more sensible for long-latency operations
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Show only one write to the destination register, not two.
2017-06-28 02:09:18 -07:00
6f8fdff762
Basic L1 D$ ECC support
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Only supports ECC on data, not tags; only supports byte granularity.
2017-06-28 02:09:18 -07:00
6100600179
Minor D$ code cleanup
2017-06-28 02:09:18 -07:00
3e04a99f61
Refactor frontend exception passing
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Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
2017-06-28 02:09:18 -07:00
cc2f87c214
Forbid S-mode execution from user memory
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285c81746f
2017-06-28 02:09:18 -07:00
8aa16a11f3
Reduce D$ access energy when refill width > access width
2017-06-28 02:09:18 -07:00
25f585f2a9
Remove unused signal from TLB interface
2017-06-28 02:09:18 -07:00
d5f80df0ae
Allow speculative I$ refill to cacheable regions
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Backpedaling on 27b143013f
2017-06-28 02:09:18 -07:00
e1fe0f245b
debug: Don't reset debugint register, as none of the interrupt registers are.
2017-06-27 14:10:13 -07:00
136e4b6c27
debug: use consistent coding style (Reg(init ... ) vs RegInit)
2017-06-27 13:42:38 -07:00
3b9550ede3
debug: correctly declare reg_debugint
2017-06-27 13:42:38 -07:00
56839b2c62
debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec)
2017-06-27 13:42:38 -07:00
665c2a349c
Correct Debug + WFI Interactions
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1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
2017-06-27 13:42:38 -07:00
c9cfe46604
rocket,Rocket: fix type mismatch ( #819 )
2017-06-27 11:22:08 -07:00
aced18b3bb
Move RoCC interface to Diplomacy and TL2 ( #807 )
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* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
6b79842e66
dcache: just left shift by untagbits to get tag
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Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
f396b4142d
Merge pull request #806 from freechipsproject/mulh
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Improve integer mul/div
2017-06-20 13:01:16 -07:00
675f183dd2
refactor ICache to be reusable by other frontends ( #808 )
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* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
2017-06-20 08:21:01 -07:00
a6d9884cc0
Improve integer mul/div
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- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
2017-06-19 12:09:21 -07:00
61c39da475
Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 10:49:36 -07:00
8552c77972
Fix I$ reset regression FU-357
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Can't rely on s2 TLB response, so mask using s2_valid.
2017-06-09 00:48:24 -07:00
16ecbdd5b2
Reduce fanout on critical I$ miss signal
2017-06-02 20:45:50 -07:00
27b143013f
Improve ITLB QoR
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- No need to check cacheability
- Remove a gate delay from PMP path
2017-06-02 20:45:50 -07:00
