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Commit Graph

136 Commits

Author SHA1 Message Date
5bd9f18e5b rocket: add dts cpu description 2017-03-02 21:19:22 -08:00
0b950b5938 coreplex: bind assigned resources 2017-03-02 21:19:19 -08:00
3931b0faff coreplex: assume L1 runs no slower than L2 2017-02-17 15:15:41 +01:00
e8c8d2af71 Heterogeneous Tiles (#550)
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
d1744a5667 coreplex: zero memory channels is also allowed 2017-02-03 19:00:08 -08:00
b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
2017-02-03 17:19:21 -08:00
93b2fa197e Artefact output (#545)
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
2017-02-02 19:24:55 -08:00
280af9684b BankedL2Config: use the same LazyModule for all L2 banks
This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
2017-01-30 14:02:59 -08:00
24ee7f45f5 rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
03f2fe02ac coreplex: support rational crossing to L2 (#534) 2017-01-27 17:09:43 -08:00
3fc55298ef coreplex: provide coherence managers with geometry information 2017-01-23 15:50:39 -08:00
38c9ddffcc BankedL2: move TLFilter BEFORE coherence manager
This lets smart caches exclude the sets that are filtered.
2017-01-21 13:23:07 -08:00
dcadd5a006 coreplex: move TLBuffers for L2 and socBus 2017-01-20 22:23:36 -08:00
3a5e5a65f8 coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
258abc5629 coreplex: re-enable stateless L2 config 2017-01-19 19:07:14 -08:00
bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
e0411c6cde [coreplex] bugfix: re-enable multicore configs via WithNCores 2017-01-19 17:48:04 -08:00
307f938b88 [rocket] bugfix: fixes #517 2017-01-19 17:48:04 -08:00
9a6634cd40 Add TLBuffers on the L1 backends and blind exit points (#513)
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
2017-01-17 11:57:23 -08:00
74b6a8d02b Refactor Tile to use cake pattern (#502)
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
52bb6cd9d9 Configs: use a uniform syntax without Match exceptions (#507)
* Configs: use a uniform syntax without Match exceptions

The old style of specifying Configs used total functions.  The only way to
indicate that a key was not matched was to throw an exception.  Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup.  The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
2017-01-13 14:41:19 -08:00
020fbe8be9 diplomacy: make config.Parameters available in bundle connect()
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
f3d0692619 Make a directory for the config package (#464)
* [config] make dir structure mirror packages

* [config] expunge max_int
2016-12-05 10:42:16 -08:00
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
a17753983a coreplex: allow legacy devices to override the config string (#458) 2016-11-25 19:38:24 -08:00
2b80386a9e rocketchip: TileInterrupts needs a TLCacheEdge (#456) 2016-11-25 17:02:29 -08:00
0baa1c9a45 coreplex: CacheBlockOffsetBits was wrong!
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.

I don't understand how this very serious bug did not cause problems before.
2016-11-24 18:32:44 -08:00
9f1c668c4f config: when modifying Parameters, subordinate lookups use top 2016-11-23 20:44:45 -08:00
dae6772624 factor out common cache subcomponents into uncore.util 2016-11-23 12:09:35 -08:00
13190a5de0 rocketchip: re-add AXI4 interface 2016-11-22 17:27:58 -08:00
c230580157 coreplex: rename RocketPlex => RocketTiles 2016-11-22 17:27:58 -08:00
bbabcf67ff coreplex: width adapter should happen as part of coherence manager
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
2016-11-22 17:27:58 -08:00
3d644b943c coreplex: configString is a property of the RISCVPlatform 2016-11-21 21:13:26 -08:00
e8be365b5d rocketchip: remove GlobalAddrMap completely 2016-11-21 21:13:26 -08:00
d1328a6b6f rocketchip: remove most uses of GlobalAddrMap 2016-11-18 19:38:02 -08:00
001d9821bd Merge remote-tracking branch 'origin/master' into tl2-tile 2016-11-18 18:19:41 -08:00
be8121eeaf coreplex: fix clock crossing 2016-11-18 17:15:57 -08:00
0082d713af coreplex: disable Stateless config until we implement adapter 2016-11-18 16:23:16 -08:00
a6188efc41 rocketchip: break infinite Config loops 2016-11-18 16:18:33 -08:00
37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
bab504cc3f Add various granular and composable configs. 2016-11-18 11:30:07 -08:00
179c93db42 tilelink2 broadcast: make it controlled via Config 2016-11-17 17:26:49 -08:00
c82b371354 rocketchip: remove obsolete TL1 config 2016-11-17 14:24:45 -08:00
dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
24e3216fcf coreplex: allow zero interrupt sink/sources 2016-11-16 16:50:36 -08:00
06a7b95d0d tilelink2 broadcast: support bufferless Config 2016-11-16 12:25:11 -08:00
10e459fedb rocket: change connection between rocketchip and coreplex
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
71315d5cf5 WIP scala compile and firrtl elaborate; monitor error 2016-11-11 13:07:45 -08:00
32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem 2016-11-04 13:36:47 -07:00